masterplayer/adxl345-sv

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device

adxl345-sv's Issues

Unite ACT with TAP requests for FSM work optimization

FreeFall interrupt support in hw/sw processing

Issue with multidriven nets in version 1.3

WATERMARK interrupt support in hw

Error in reading all device registers : Last register FIFO_STATUS not readed

DoubleTap interrupt processing in hw

Some pricnciples of processing as #22 #23, but need other parametrization for double tap generate event

testing in hw

Measurement testing required for Interrupt processing on software

For estimation performance we need measurements about how fastly interrupts processed in processor in classical variant and how fastly processed with this component

SingleTap interrupt processing in software

Add interrupt processing for SingleTap interrupt

problem with assignation register file

writing to register, when component await data might no effect

DoubleTap processing in sw

for #25 implementation need to change in interrupt processing

add interrupt signal to component

FIFO interrupt processing support

There are needed for special processing for FIFO interrupts, because sw must read series of samples.
Possible mechanism may be realized as next scheme:

add support for single requests from ps to adxl devices for reading

it allow perform interrupt processing

rework API for work with component

Optimize FPGA structure

Update documentation

Software API can perform calibration process

Calibration includes next steps :

1. Read current data N times
2. Calculate average for this times
3. Round them
4. Update OFSX, OFSY, OFSZ registers in device

Calibration completed

or not?

add documentation

AutoCalibration support in hw

Need to support auto calibration of device

OVERRUN interrupt support in hw

realize api for software access to register

add register map

Optimal request interval calculation and assign to register in config space

Update software processing

Add mechanism for output rules

Output rules may be next :

1. X, Y, Z as int16 values, readed directly from device
2. X, Y, Z as float value, msmt in gravity values
3. roll & pitch values

add this functional for axi_adxl structure and realize changing procedure on API

Need FSM correction

Because Reading data [0x32..0x37] or reading INT_SOURCE[0x30] register makes clear the data

Interrupt can work only when hw device not request data.

Solution :
After device configuration, we need disable request (reading data from device), but stay in ability to send the data independently of ENABLE signal in configuration register.
And DISABLE in CTL reg not reset the internal device memory.

INACTIVITY interrupt support in hw/sw

New Issue: need_update memory in adxl345 component isn't deassert after sending data to device

it causes a next events :

1. new data for sending received
2. update_request asserts to 1
3. FSM in IDLE_ST and analyzes need_update_reg
4. internal logic sending request to device when need_update_req[address] = 1
5. internal logic analyze other bits in memory
6. internal logic sends old requests to device

solution :
maybe, after new command was sended, need_update_reg[address] has no deassertion event.

Interrupt processing in hardware extension

Need add support for interrupt processing in hardware, it might be additional state in finite state machine

Algorithm: (hardware)

1. INTR signal asserted
2. FSM goes from IDLE to send request for reading
3. await for read data finalize
4. Process interrupt : AND INT_SOURCE and INT_ENABLE. Different interrupts can be processed differently : some of reading registers 0x32-0x37, some as send INT_SOURCE registers for clean up interrupts
5. Generate interrupt signal for processing system

software :

1. await for interrupt
2. if interrupt, read device registers
3. make actions for processing interrupts(printing, accumulation, etc)
4. send ack to configuration bank for deassertion irq signal from ip core

SingleTap Interrupt processing in hw

add ability of component for processing in hardware SingleTap interrupts

DataReady interrupt processing in hw/sw support

ACT_TAP_STATUS requesting in SingleTap/DoubleTap interrupts

need checking about INTR signal connected correctly

how do this :
Invert INTR signal over writing to DATA_FORMAT register

ACTIVITY interrupt processing in hw

sw supports for ACTIVITY interrupts