matthewluo7/involutionnet

This repository is our 3rd place work in the 59th IEEE/ACM Design Automation Conference System Design Contest.

InvolutionNet

Introduction

This repository is our 3rd place work in the 59th IEEE/ACM Design Automation Conference System Design Contest. A fully-pipelined FPGA accelerator for object detection CNN is designed in Vivado High-Level Synthesis. The design is deployed on an embedded FPGA, Ultra96-V2, and is evaluated according to its inference speed, energy consumption and prediction accuracy. In July 2022, the final result of the contest was announced at the 59th IEEE/ACM Design Automation Conference, San Francisco, USA.

Team Members

• Haitong Huang, State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences
• Erjing Luo, School of Information and Electronics, Beijing Institute of Technology
• Cangyuan Li, Center for Intelligent Computing Systems, Institute of Computing Technology, Chinese Academy of Sciences

Repository Organization

• deploy: the deployment files on Ultra96-V2
• scripts: the scripts for generating HLS and Vivado project
• src: the accelerator design

involutionnet's Issues

D in batch normialization/quantization

Hi there,

Would you explain the D in the bn_qurelu_fixed function? What are the equations for the quantization of the final output? What is L_shift?

请问是基于ultranet改进的吗？

On board running problem

Hello,

I tried to follow your work and recover from the start, and i have finishe the hls part with the sim and co-sim passing and generate the verilog based ip.
But when generating the bit file and stream it to the board, it stalls in
dma.sendchannel.wait()
dma.recvchannel.wait() part.
I want to know how to check it works or not. And i am curious that you are using a c based load_image function. Do i need to compile from the board?
and also about these block, how to find the register address？ will that affect the running ?
nn_ctrl.write(0x0, 0) # Reset
nn_ctrl.write(0x10, in_buffers[which_buffer].shape[0])
nn_ctrl.write(0x0, 1) # Deassert reset

Thanks alot

How to realize multi-classification?

Hi there,

We have studied your design. It is a very nice job! However, when we want to implement a multi-classification task, we found your design is not supportive. Is your design based on the ultranet before? Any advice to help the multi-classification task work?