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View Code? Open in Web Editor NEW"Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.
License: GNU General Public License v3.0
"Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.
License: GNU General Public License v3.0
VHDL ile FPGA programlama serisi ders 18'de uart alım yaparken stop bitinin tamalanmasını beklemeden, son stop bitinin tam ortasında rx_done_tick_o çıkışı 1 yapılıyor. Full-dublex kullanılıyorsa hiç bir problem yaratmayacaktır ancak half-dublex kullanıldığında bazı özel durumlarda veri transferinde hata oluşabilir.
Hello,
Thank you for your lessons they are very helpful for us, i just found out about them.
I was playing around with the axi uart full, I integrated it into my microblaze design and I would like to know if you have a little software that do the send stop read write functions.
I'm very new in the VHDL world (not even 6 discontinued months of experience) thus i can't help to figure out how to do software for a custom IP.
Kind regards.
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