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UESTC--DigitalLogicDesign

Something just no fun XD Digital logic design Homework

DigitalLogicDesign-Exp

Test1

  1. 3-8 译码器 74x138 的设计和实现。
  2. 4 位并行进位加法器 74x283 的设计和实现
  3. 两输入 4 位多路选择器 74x157 的设计和实现。
  4. 要求使用两种不同的描述方法完成(门级描述与行为级描述)

Test2

  1. 设计边沿 D 触发器 74x74。
  2. 设计通用移位寄存器 74x194。
  3. 采用 1 片 74x194 和其它小规模逻辑门设计 3 位 LFSR 计数器。
  4. 设计 4 位同步计数器 74x163。
  5. 要求使用两种不同的描述方法完成(门级描述与行为级描述)

Test3

  1. 设计一个 8bit ALU,实现两个 8bit 二进制数的算术运算和逻辑运算,
  2. 算术运算(加、减);
  3. 逻辑运算(与、或、置 1、清 0);

Test4

  1. 字扩展和位扩展的方式,设计一个 32X8 的静态存储器,能够对其随机的读写,其中32代表地址的寻址空间大小,8表示数据单元的位数

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