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View Code? Open in Web Editor NEWA highly optimized single producer single consumer message queue C++ template
License: MIT License
A highly optimized single producer single consumer message queue C++ template
License: MIT License
Hi,
I am trying to figure out the portability / correctness of SPSCQueue.h on different architetures, especially armv8.
For this, I am mostly going by https://www.kernel.org/doc/Documentation/memory-barriers.txt
My understanding is that both pop / push obviously need to happen in correct order / atomic.
I am familiar with
__asm__ volatile("" ::: "memory")
to enforce a compiler level barrier and
__asm__ volatile ("mfence" ::: "memory")
to actually enforce a cpu barrier at runtime.
This should boil down to _mm_mfence (x86) or __mf (arm).
It's not clear to me how, e.g.
asm volatile("" : "=m"(data) : "m"(read_idx) :); // memory fence
enforce a barrier at runtime.
Is this the case because x86 has a more or less strict memory ordering, and the ops are atomic (are they?)? Or is a full memory fence simply not needed in this case.
Also: How portable is this to architectures with weak memory ordering, e.g. to armv8?
Would std::atomic_thread_fence be needed as replacement? I see you used that at the beginning before replacing it with the asm instructions.
Many thanks for your efforts! :-)
机器配置:Gold 6144 3500MHZ,同一个node上面隔离出来2个CPU 绑核做的测试。
请问你的机器配置是啥能跑到50-100ns?或者需要做些其他的配置?
你好, 我测试了SPSCQueue.h的代码,发现前CNT条消息,收不到?要写满CNT条消息后,消费者才能读取到第1条消息
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