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View Code? Open in Web Editor NEWA superscalar RISC-V CPU with out-of-order execution and multi-core support
License: MIT License
A superscalar RISC-V CPU with out-of-order execution and multi-core support
License: MIT License
Hi, I can't find any source code about debug module, it seems that this project didn't implement it.
tags are allocated in-order, so the write-back sequence must be in-order too
Implement following [h]pmcounterX:
instret: Retired instruction
pmcounter3: IF cache misses
pmcounter4: Cached load
pmcounter5: Cached store
pmcounter6: Cached load misses
pmcounter7: Cached store misses
pmcounter8: Uncached load
pmcounter9: Uncached store
pmcounter10: In-flight instruction saturated cycles
pmcounter11: Issue stall cycles (Stalled by a full reservation station, or the in-flight limit is reached)
pmcounter12: Issue FIFO empty cycles
pmcounter13: ROB empty cycles
pmcounter14: Retired branch count
pmcounter15: Retired branch misperdicts
pmcounter16: Issued BHT misses
pmcounter17: Issued RAS misses
pmcounter18: Exceptions
pmcounter19: X_CALL exceptions
pmcounter20: Interrupts
This is to make cached writes finish within one cycle
Also, LSBuf now only hold one instruction (Length = 2, without maybe_full)
This will also likely affect the delay of default branch prediction and RAS pop
Currently, each instruction goes through a 1 tick delay before entering the CDB. This can cause severe slowdown running code with many RAW hazards.
The 1 tick delay may be unnecessary for some functional units with less delay by its own, such as ALU, Branch and Bypass.
No Makefile Found In Root,
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