mfkiwl/100g-fpga-network-stack-core

This repo contains the Limago code

100 GbE TCP offload Engine

This repository implements from OSI layer 3 to above and is part of Limago. To generate the complete stack please refer to Limago

Prerequisites

Make sure that Vivado-HLS is in the PATH and you are running a supported version

• Vivado-HLS 2018.2 to Vivado-HLS 2020.1

If you are not sure what version is running execute the following command:

vivado_hls -version

Getting Started

Execute make in the root folder, a new folder named synthesis_results will be created. After the folder creation the project will launch the Synthesis of the different IP-Cores. Be patient this may take around 10 minutes.

Explore the IP-Cores

You can check the synthetized project under synthesis_results. For instance, if you want to open the TOE

vivado_hls -p synthesis_results/TOE_hls_prj/

Citation

If you use the TCP/IP stack or the checksum computation in your project please cite one of the following papers and/or link to the github project:

@inproceedings{sutter2018fpga,
    title={{FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks}},
    author={Sutter, Gustavo and Ruiz, Mario and L{\'o}pez-Buedo, Sergio and Alonso, Gustavo},
    booktitle={2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
    year={2018},
    organization={IEEE},
    doi={10.1109/RECONFIG.2018.8641729},
    ISSN={2640-0472},
    month={Dec},
}
@INPROCEEDINGS{ruiz2019tcp, 
    title={{Limago: an FPGA-based Open-source 100~GbE TCP/IP Stack}}, 
    author={Ruiz, Mario and Sidler, David and Sutter, Gustavo and Alonso, Gustavo and L{\'o}pez-Buedo, Sergio},
    booktitle={{2019 29th International Conference on Field Programmable Logic and Applications (FPL)}}, 
    year={2019},
    month={Sep},
    pages={286-292}, 
    organization={IEEE},
    doi={10.1109/FPL.2019.00053},
    ISSN={1946-147X}, 
}

License

This project is a collaboration between the Systems Group of ETH Zürich, Switzerland and HPCN Group of UAM, Spain. Furthermore, the starting point of this implementation is the Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware by Sidler, D et al. The original implementation can be found in their github.

For this project we keep the BSD 3-Clause License

BSD 3-Clause License

Copyright (c) 2019, 
HPCN Group, UAM Spain (hpcn-uam.es)
Systems Group, ETH Zurich (systems.ethz.ch)
All rights reserved.


Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright notice, this
  list of conditions and the following disclaimer.

* Redistributions in binary form must reproduce the above copyright notice,
  this list of conditions and the following disclaimer in the documentation
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* Neither the name of the copyright holder nor the names of its
  contributors may be used to endorse or promote products derived from
  this software without specific prior written permission.

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