Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.
License: GNU General Public License v3.0
Tcl 0.14%Assembly 0.02%VHDL 1.10%Verilog 98.74%
risc-v's Introduction
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* RISC-V PROJECT
* TESSER ANDREA VIANELLO NICOLA
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Folder's organization:
innovous: contains all the useful files and reports generated during and after the
place-and-route phase in Cadence Innovous environment.
conn.rpt and geom.rpt show the successful outcome of the verification phase.
The netlists generated at the end of the process are saved in verilog format as:
RISCV_pr_standard.v and RISCV_pr_custom.v
final_report: The final technical report of our work in pdf format.
scripts: Scripts used for simulation, synthesis and place-and-route
sim: Source code (.asm) and binary (.hex) of the programs used for the design verification
src: Here all the files that compose the design are stored.
In the tb subfolder there are all the files used in the testbench.
syn: Inside it you can find: reports for area, timing, power and switching activity;
.sdc and .sdf files; the verilog synthesized netlist.