mjlyons/vspi

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

vspi's Issues

txMem missing ports?

Hi,
your txMem doesnt have tx_mem_addr_valid?
and also the tx_mem_data_valid ports?

how can you know when to read the buffer data, and also when the buffer data is ready?

spiifc mySpiIfc (
.Reset(Reset),
.SysClk(SysClk),
.SPI_CLK(spi_clk),
.SPI_MISO(spi_miso),
.SPI_MOSI(spi_mosi),
.SPI_SS(spi_ss),
.txMemAddr(spi_addr),
.txMemData(spi_data),
.rcMemAddr(spi_rcMem_addr),
.rcMemData(spi_rcMem_data),
.rcMemWE(spi_rcMem_we),
.debug_out(debug_out)
);