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Morten Borup Petersen's Projects

better-enums icon better-enums

C++ compile-time enum to string, iteration, in a single header file

calyx icon calyx

Intermediate Language (IL) for Hardware Accelerator Generators

catch2 icon catch2

A modern, C++-native, header-only, test framework for unit-tests, TDD and BDD - using C++11, C++14, C++17 and later (or C++03 on the Catch1.x branch)

circt icon circt

Circuit IR Compilers and Tools

clang-tools-extra icon clang-tools-extra

Mirror of official clang-tools-extra git repository located at http://llvm.org/git/clang-tools-extra. Updated every five minutes.

coremark icon coremark

CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).

dbdm icon dbdm

Displacement Based Dynamic Memory

images icon images

Docker images for the CIRCT project

llvm-project icon llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

mlir-interactive icon mlir-interactive

Qt based UI for visual and interactive composition and execution of MLIR compilation flows.

netcracker icon netcracker

NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between switchboxes

qtwasmthreaded icon qtwasmthreaded

Prebuilt version of the latest Qt for WebAssembly, with thread support enabled

ripes icon ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

rtoc icon rtoc

a Real-Time Object Classifier

sparseaddressspace icon sparseaddressspace

A datastructure for efficiently simulating a (potentially unlimited) address space.

velonacore icon velonacore

A VHDL implementation of a single-cycle Leros core

verilator icon verilator

Verilator open-source SystemVerilog simulator and lint system

vsrtl icon vsrtl

Visual Simulation of Register Transfer Logic

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