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Morteza Rezaalipour

FPGA/ASIC (Verilog/VHDL) Enthusiast | Low Power Approximate Computing | PhD candidate at USI | Part-time Teacher

As a PhD candidate in VLSI and computer architecture, I specialize in low-power circuit development for image and video processing and machine learning, focusing on approximate computing as a new computing paradigm. My background includes a strong research record and hands-on experience, notably with the University of Utah. Skilled in conveying complex ideas in native-level English, I am a fast learner, adaptable, dynamic, and motivated. With a positive outlook, I am keen to bring my expertise in approximate logic synthesis to the industry, applying my skills to address real-world challenges and drive technological progress.

LinkedIn       ReaserchGate       Google Scholar

🧰 Languages and Tools

Python

C/C++

MATLAB

Verilog

VHDL

Git

Linux

GitHub

Bash


📊 Stats

MortezaRezaalipour's Stats

Morteza Rezaalipour's Projects

axmap icon axmap

AxMAP: Making Approximate Adders Aware of Input Patterns

erroreval icon erroreval

This is the open source code for our paper titled "ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing"

verilogchecker icon verilogchecker

A circuit equivalence checker given an error threshold for Approximate Computing

verilogpadanalyzer icon verilogpadanalyzer

VerilogPADAnalyzer is a Python application designed to analyze and report the Power, Area, and Delay (PAD) of Verilog input circuits.

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