mortezarezaalipour/verilogpadanalyzer

VerilogPADAnalyzer is a Python application designed to analyze and report the Power, Area, and Delay (PAD) of Verilog input circuits.

Morteza Rezaalipour

FPGA/ASIC (Verilog/VHDL) Enthusiast | Low Power Approximate Computing | PhD candidate at USI | Part-time Teacher

As a PhD candidate in VLSI and computer architecture, I specialize in low-power circuit development for image and video processing and machine learning, focusing on approximate computing as a new computing paradigm. My background includes a strong research record and hands-on experience, notably with the University of Utah. Skilled in conveying complex ideas in native-level English, I am a fast learner, adaptable, dynamic, and motivated. With a positive outlook, I am keen to bring my expertise in approximate logic synthesis to the industry, applying my skills to address real-world challenges and drive technological progress.

           

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verilogpadanalyzer's Issues

Standard module name in verilog files

It can happen that verilog files generated from different methods (such as MECALS) do not contain the correct module name, which consequently breaks the parsing of the information in the files. I developed a quick solution to specify the models correctly from their names.

I called the file 'specify_module.py' for now.

import os
import sys
from tempfile import mkstemp
from shutil import move, copymode

verilog_path = sys.argv[1]

input_list = os.listdir(verilog_path)

for file in input_list:
    subst = file[:file.rfind('.')]
    file_path = f'{verilog_path}/{file}'
    fh, abs_path = mkstemp()
    with os.fdopen(fh,'w') as new_file:
        with open(file_path) as old_file:
            for line in old_file:
                if 'module' in line and 'endmodule' not in line:
                    splt = line.split()
                    second = splt[1]
                    new_file.write(line.replace(second, subst))
                else:
                    new_file.write(line)
    copymode(file_path, abs_path)
    os.remove(file_path)
    move(abs_path, file_path)

The code simply requires the path to where the verilogs are saved and will update all the existing files with the correct module name.

Example use case:

$ python3 specify_module.py [path-to-verilogs]

will setup the files correctly.

Yosys/abc fails when this project is used as a PyPI pacakge!

When running:

python3 test.py abs_diff_i4_o2.v

I get the following error!

/usr/lib/python3/dist-packages/requests/__init__.py:89: RequestsDependencyWarning: urllib3 (2.0.7) or chardet (3.0.4) doesn't match a supported version! warnings.warn("urllib3 ({}) or chardet ({}) doesn't match a supported " Traceback (most recent call last): File "test.py", line 10, in <module> main() File "test.py", line 6, in main syn_obj.get_area() File "/home/usi/.local/lib/python3.8/site-packages/vpadanalyzer/synthesis.py", line 38, in get_area raise Exception(f'Yosys ERROR!!!\n {process.stderr.decode()}') Exception: Yosys ERROR!!! ERROR: Can't open ABC output file "/tmp/yosys-abc-9rAjmt/output.blif".