This repository acts as a meta-repository for a BlackParrot FPGA design. The design methodology is to package a BlackParrot processor as an IP block that can be directly instantiated within a Vivado Block Design using the Vivado IP Integrator methodology. An FPGA host block is similarly packaged for instantiation in the design. The BlackParrot I/O ports are connected to the BlackParrot FPGA Host and BlackParrot's memory interface is connected to an AXI network with a memory that acts as BlackParrot's private DRAM. The other side of the host can be connected to the a PCIe XDMA IP block that can be opened from a host PC to issue control commands to the BlackParrot processor.
The provided design requires Vivado 2019.1 and targets a VCU128 (vu37p ES1) board. However, the approach can be easily adopted to any FPGA device and board as all interfaces to the BlackParrot IP blocks are AXI4.
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