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License: MIT License
Highly configurable Beaglebone PRU-based DDS
License: MIT License
We will still be using UIO for PRU access rather than remoteproc, but the assumptions that are made based on old linux images need to be removed.
pru-dds lacks a CW modulator. This should be simple.
pru-dds could very well function as the VCO, VCA, and ringmod sections of a musical synthesizer. I know how to do alsa midi, so this shouldn't be a giant problem.
Hi, I have managed to run the pru-dds, and it runs without complains. But if I run it with frequency set to 10kHz and connect oscilloscope to any of the outputs, I see no signal at all. I was expecting some high/low jumps. Any idea where I can look to find out what is wrong?
Thanks
I'm trying to get a double-buffered PRU setup to allow a stepper motor program to write precisely timed byte streams to an output port. I compute all the step/dir pulses, in advance, (github.com/omnister/velo) and would like to stream them using the PRU. It looks like your program almost does just what I want. Do you have a ring-buffer so that the driver program can fill the PRU memory on the fly just ahead of the output pointer? I can see that you do repetitive wavetables - for my application, I need a continuous stream. Sorry to open an issue, I searched diligently but couldn't find any email for you in the docs.
Rick Walker ([email protected])
pru-dds lacks an FM modulator.
am.p and dsb.p should have at least a basic averaging antialiasing filter. There's 24976 instruction cycles at the beginning of the loop to implement a delay, so there should be plenty of time to do it.
pru-dds should have a PRU program to do binary PSK that has a way for the user to set symbol rate, basically the time to transition through one cycle of the raised cosine filter, or from
0x00002250 to 0x00002750 in the wavetable (or vice versa); and a way to signal a phase reversal should occur NOW. One a phase transition begins, it should be unstoppable and further requests for a phase transition should be ignored until the current one is complete. Should be pretty simple, the hard part is really deciding when we're done with a phase reversal. Perhaps when
curpos - where_i_should_be < skiplen? The second branch of that (the else) doesn't need to contain the exact same cycle count as the first, and can just set whatever flag initiates a reversal to zero.
When this is complete pskstream.c should perhaps be rewritten to use it instead of the dsb modulator.
Hi Brad, is it possible to create a pcm clock soruce with your prupdds
PCLK:
512 kilohertz = 5120000
1.024 megahertz = 10240000
2.048 megahertz = 20480000
VD = 3.13 to 5.25 V
PCLK Duty Cycle Tolerance: Min 40%, typical 50%, max 60%
PCLK-to-FSYNC Jitter Tolerance: -120ns, typical 0ns, Max 120ns
Rise Time: PCLK max 25ns
Fall Time: PCLK max 25ns
Thanks,
Nathan C
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