nealcrook/multicomp6809

Software and modifications for Grant Searle's multicomp FPGA design, mostly focussed towards the 6809 variant: Forth (CamelForth), FLEX, CUBIX, NITROS9, FUZIX and the exec09 emulator.

DOCUMENTATION
For instructions and other documentation for these files, refer to the Wiki (use the link at the top of the page). You might not see the link if you are using a mobile device -- you may need to select "desktop version"

I always wanted a 6809 machine. I still have the A4 notebook where I sketched out design ideas. However, I never simultaneously had the time and money to build one from scratch (even though I have accumulated all of the parts in my junk box over the years).

When I saw this http://searle.hostei.com/grant/Multicomp/index.html I realised I could satisfy my yearning without too much soldering.

I decided that I would run Brad Rodriguez's Camelforth on it. Before I did that I resussitated a 6809 emulator and added crude support first for Brad's "scroungmaster" machine and then for the 6809 multicomp machine. That emulator is https://github.com/nealcrook/exec09.

Camelforth is currently running on real hardware. Using a hardware bank-switching unit on multicomp Camelforth can also act as boot loader for Grant's port of Microsoft ROM BASIC and for the N8VEM port of Dave Dunfield's CUBIX and for my ports of FLEX, NitrOS-9, BUGGY and FUZIX. All of this also runs on exec09.

This repository is a venue for sharing the hardware and software that I have used on my multicomp.

For detail on how to use any of this stuff, click on the "wiki" button on the right.

More on CamelForth here: https://launchpad.net/camelforth http://www.camelforth.com/ http://www.bradrodriguez.com/papers/index.html

Approximate WIKI Change Log:

03Feb2016 Rework FLEX stuff to add more detail and make it clearer

05Feb2016 Rework CUBIX stuff to describe new single-step boot. Remove references to obsolete SDINIT.

12Feb2016 New BUGGY source code - single step now works. Expanded WIKI pages on CamelForth to add some links on tutorials. New versions of TERMINAL and UART VHDL to add functional reset of input FIFOs to avoid some start-up problems.

09Aug2018 Tidy-up pass - adding a few misisng files and scripts and generally tidying things up. In particular, clean up the build process for the 6809 ROM BASIC and add some images for simulation debug.

06Mar2019 Reorganisation to try to provided consistent descriptions for each operating environment: the original material evolved over time as I ported successive bits of code and it shows (too much) in places.

24May2020 WIKI was a mix of creole and markdown. I am gradually migrating all the pages to markdown, making various small updates on the way. Expand the pages on camelforth to describe how to build it at a different start address.

multicomp6809's Issues

Made a PCB and video

Hi Neal,

I made a PCB that uses an inexpensive ($20ish on AliExpress plus shipping) QMTECH FPGA card that runs everything. The card is up for sale on Tindie.

Also put together a short video.

Thanks!

Doug

Serial-only use?

Hello - I'm trying to bring up your 6809 config on a bare EP2C5 with just a serial FTDI adapter connected.
The reason is that the RAM chip isn't working yet (I suspect a faulty A7 addr on pin 143, easily adjusted later).
To help with troubleshooting, I've rebuilt a minimal system - the goal is to first get 6809 + CamelForth going.
From there, it will hopefully be easier to work through the remaining issues one by one.

Looking through the chromium.lst blocks, I see SCCINIT calls, so presumably both UARTs are being inited.
But I can't figure out whether they also act as alt console, if there is no PS/2+VGA hardware present (yet)?

Microsoft basic/Nitros9

Hi Neal, just compiled and succesfully have a full 1mb version of your build working on my DE0 Nano. Question I have is for specifically Basic & Nitros9. Do I make an image file on the SD for Grants Microsoft Basic? And also for Nitros9 I can definitely help with the port across for Level 2, as I helped create it in the first place. Kernel files are the only mods needed for your MMU and Timer IO.

Bill Nobel

Microcomputer4 Build failed

I did a fresh clone and tried building Microcomputer4. I got the following error:

Error (10344): VHDL expression error at Microcomputer.vhd(405): expression has 3 elements, but must have 7 elements
Error (10346): VHDL error at Microcomputer.vhd(394): formal port or parameter "cpuAddr" must have actual or default value

Line 405:

   cpuAddr => cpuAddress(15 downto 13),

MEM_MAPPER2.vhd has:

    cpuAddr : in std_logic_vector(15 downto 9);

Bringing up multicomp stuff on RetroShield6809

Hi Neal,

Would it be possible if I reuse some of your OS files on my open-source hw project? I didn't see a license file, so wanted to check with you.

I started an Arduino project called "RetroShield for Arduino Mega":

www.8bitforce.com/projects/retroshield
www.gitlab.com/8bitforce/retroshield-hw
www.gitlab.com/8bitforce/retroshield6809

Basically I hooked up a 6809 to Arduino Mega and emulate all system hw in Arduino except the real processor executes code. Similar to your fpga design. I ported the Buggy monitor code that I modified for my older Simon6809 project. Next step is to port the Flex09. Ultimate goal is to use SDCard as HDD and a VGA/Keyboard shield for Arduino for a stand-alone computer :)

If you like to bring up the OS together, I'll be up for that too.

Thank you,
Erturk

The procedure contained in camelforth/mmu_test.txt seems to blow up

As you know I am trying to port multicomp6809 to the Altera DE1. I wanted to see if the MMU and my sRAM wiring logic was working properly after my changes and found the code in camelforth/mmu_test.txt. Unfortunately when I run this everything works until:

789A FDFF !  \ write to RAM block 6

After this CamelForth seems to blow up, not recognizing any words after this. So I can't tell if the MMU or sRAM wiring correct or not because I can't do any further debugging after this.

If I do different tests which don't do any manipulation to the ROM area then it seems the MMU is working and addressing ram correctly:

HEX
MMUMAP
: W8 40 8 DO 24 FFDE ! I FFDF C! I 8000 C! LOOP ;
: R8 40 8 DO 24 FFDE ! I FFDF C! 8000 C@ . LOOP ;
: RA 40 8 DO 25 FFDE ! I FFDF C! A000 C@ . LOOP ;

Running those I see 0x08 through 0x3F and no repeats, so I'm assuming the MMU and RAM Mapping logic are working? Any additional hints?

Is S" working correctly?

Hi Neal,

Good to see you've still been improving the documentation on this repository, recently.

As I'm creating a target image for my Vectrex 6809, I'm using S" to lay down a text string. However, I don't quite understand what I'm seeing, maybe you can shed some light? My test code is:
HERE EQU HELLO-WORLD-STRING
S" HELLO WORLD" 80 C,
S" HELLO WORLD123" 80 C,

The 80 is used by the Vectrex to terminate a string. For a Vectrex BIOS call to print a string, I would expect to add one to the start address of the string to avoid the length byte . Instead, I have to add three!?

If I take a look at the ROM, I get this (length byte indicated by ^):

Before the length byte, for both the strings, I'm seeing "0B B0". If I look at addres $0BB0 in the target ROM, it's the first bytes of (S") (I think than's the CFA?):

This seems wield, why does it need (S") once the string is compiled? Does that look right to you?

I'll soon be releasing my Vectrex Forth, I have completed the Forth to Vectrex BIOS API, now I'm just cleaning up the code before making my repository public. This S" query is part of it taht clear up!

Regards,
Phil

Trying to build Nitros-9

Hello Neal,

I've been following the steps outlined at https://github.com/nealcrook/multicomp6809/wiki/NitrOS-9 - it's not reaching the end out of the box. The make PORTS=mc09 terminates with this message:

cat ../modules/ioman ../modules/rbf.mn ../modules/dds0_80d.dd ../modules/mc09sdc.dr ../modules/s0_80d.dd ../modules/s1_80d.dd ../modules/s2_80d.dd ../modules/s3_80d.dd ../modules/scf.mn ../modules/mc6850.dr ../modules/term_mc6850.dt ../modules/term_mc6850_t0.dt ../modules/term_mc6850_t1.dt ../modules/pipeman.mn ../modules/piper.dr ../modules/pipe.dd ../modules/mc09clock_50hz ../modules/clock2_soft ../modules/sysgo_dd>bootfile_mc09sd

make[2]: *** No rule to make target `../modules/krn', needed by `kernel_mc09sd'.  Stop.

Somewhere in the make output, there is a line which might be related:

< os9 copy -o=0 kernel/krn . > ignored

Something similar happens for level2. A first hack to keep going was to do this:

cd level2/mc09l2/modules/
cp -a kernel/krnp2 kernel/mc09krn .
cd -

And then resume the build. This is perhaps not correct, I can't verify the result right now. It does keep make happy.
After that, I did make PORTS=mc09l2 dsk, which results in these disk images:

./level2/mc09l2/NOS9_6809_L2_80d.dsk
./level2/mc09l2/NOS9_6809_L2_80dxl.dsk

Am using lwtools 4.20 from Homebrew on MacOS (on a standard case-ignoring filesystem).

What might be going on here? Puzzling ...
-jcw

Issues with my attempt to compile

Sorry if this is the wrong way to communicate but I am having trouble compiling the project as it gives an error saying that Error (10481): VHDL Use Clause error at SBCTextDisplayRGB.vhd(295): design library "work" does not contain primary unit "SansBoldRom".
In addition I have been using the bare minimum internal Ram version to debug. Using the pof in the zip file I can run this and use Camelforth but the SD light is on (no sd card holder present at the moment?) and the reset key has no effect it appears that line is permanently low. I have got the sera line working with a terminal but the external ram is flaky will not stay consistent. If I remove the fpga board from the v1.10 board the reset symptoms are the same. As you can tell I am a newbie at this FPGA stuff but have managed to get Grant's bare bare minimum versions for the 6502 and Z80 to work as well as the multicomp08_iram version. I have ordered another FPGA board to see if this one is wonky, just waiting for arrival. Thanks Larry

Flex and nulls

Hi Neal - there are at least 2 ways to get rid of the nulls in FLEX. The best is to modify the byte at location $CC05 - TTYSET Null Count. The default is 4 - set it to zero. The second method is to use the "TTYSET" command in your FLEX startup.txt file (or anytime on the command line). TTYSET,NL=0 will set zero nulls. The downside of this method is that it will have already printed some nulls before it gets this far. Cheer, Ian.

How to test full 1M external RAM

Hi Neal,

First, thanks for your efforts. Great job and a fun project.

Got the Multicomp6809 working nicely with 1M external RAM, though not sure all RAM is detected.

I'm still exploring making SD images and am using a pre-built image from RBC repository; April2017. I've built the FPGA image from your latest GIT repository. SD image works fine; BUGGY, CUBIX, FLEX, NITROS9 & FUZIX all seem to load and run fine.

Q: FUZIX reports 512K RAM although 1M is installed. Any suggestions how one can test/verify the full compliment of RAM ? On hardware address cycle test described below, CS1 and CS2 toggles nicely, so appear connected/working correctly, but not seen any activity on CS2 (the second 512K RAM).

Incidentally, found a broken solder joint on my module affecting PIN135 that caused RAM failures (A4 was stuck). I wrote a diagnostic VHDL test to cycle all address lines and noted the FPGA was OK but PIN135 was floating. Repair made with fine wire and now RAM tests passed.

Thanks much.

Best Regards.
Johan Forrer,
Eugene Oregon.

5 volt power to keyboard could exceed maximum input voltage on Cyclone II

Hi Neal, I've been having a discussion with James Moxham about using 5V to power the keyboard instead of 3.3V. I have a KVM that wouldn't work on 3.3V so I hooked it to 5V and fitted two 3.3V Zener diodes to ground to limit the maximum voltage. I took some measurements without the Zener diodes and found there was 4.88V at the 10k pull-up resistors. I was expecting there to be diodes on the FPGA inputs to the 3.3V supply but it doesn't look like that is the case. According to the Cyclone II data sheet the absolute maximum input voltage is 4.6V and the maximum for 100% of the time is 4.0V. Have you fitted anything to limit the voltage? If you haven't you probably are risking your FPGA. BTW the limits on Cyclone IVs are 4.2V and 3.6V. Cheers, Ian.

Source code for Nitros09 port

Hi Neal,
is the source to your Nitros port available anywhere? I'd be really interested in taking a look as I'm building a few Multicomps (as soon as the PCBs arrive!). I'm also doing a non-FPGA version of the Multicomp based on the 6309 (with MMU in CPLD and using CF instead of SD) and would prefer not to have to reinvent too many wheels. Hope you don't mind me asking.
Thanks,
-Bob