ngc7331/github-actions-test

github-actions-test's Issues

[test-labeler] case-insensitive regex matching

bpu

[test-translator] 访存子系统中的异常处理

1. 请教一下load流水线中的异常具体是怎么处理的呢？返回ROB，等异常指令到达ROB队尾的时候再处理异常并清空load queue嘛？可以返回给load queue处理、清空异常load指令及之后的所有entry嘛？
2. 以及前递失败后为什么会触发重定向呢？实地址不一致的话不前递、通过load流水线向cache取数据不可以嘛？是会引发什么错误嘛？

以上两个问题在文档里写的比较散，可以帮忙总结解释一下嘛，谢谢！

[test-labeler] question for sta/std in diaptchR2s

hello, 在看diapatchR2s时，对于std uop的处理部分有些许不理解，请帮忙解释一下，具体如下：
对了LSU的 port 分布为[ld , ld, sta, sta, std, std] 即每个uop两个port,
当执行单元为 std时，通过 StorePipelineWidth 偏移得到sta对应的port (val sta = s0_out(idx - StorePipelineWidth))，
并且将std的valid信号赋值给sta (sta.valid := s0_out(idx).valid)？？ 这个是为什么？

https://github.com/OpenXiangShan/XiangShan/blob/1fcb3bc07900e8a8feb817ad58bc805434023414/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala#L238

for ((config, i) <- outer.exuConfigCases) {
    val outIndices = outer.exuConfigTypes.zipWithIndex.filter(_._1 == i).map(_._2)
    val numOfThisExu = outIndices.length
    val canAccept = io.in.map(in => in.valid && config.map(_.canAccept(in.bits.ctrl.fuType)).reduce(_ || _))
    val select = SelectOne("naive", canAccept, numOfThisExu)
    for ((idx, j) <- outIndices.zipWithIndex) {
      val (selectValid, selectIdxOH) = select.getNthOH(j + 1)
      s0_out(idx).valid := selectValid && !Mux1H(selectIdxOH, is_blocked)
      s0_out(idx).bits := Mux1H(selectIdxOH, in.map(_.bits))
      // Special case for STD
      if (config.contains(StdExeUnitCfg)) {
        val sta = s0_out(idx - StorePipelineWidth)
        sta.valid := s0_out(idx).valid
        s0_out(idx).bits.ctrl.srcType(0) := s0_out(idx).bits.ctrl.srcType(1)
        s0_out(idx).bits.psrc(0) := s0_out(idx).bits.psrc(1)
        XSPerfAccumulate(s"st_rs_not_ready_$idx", selectValid && (!sta.ready || !s0_out(idx).ready))
        XSPerfAccumulate(s"sta_rs_not_ready_$idx", selectValid && !sta.ready && s0_out(idx).ready)
        XSPerfAccumulate(s"std_rs_not_ready_$idx", selectValid && sta.ready && !s0_out(idx).ready)
      }
      else {
        in.zip(selectIdxOH).foreach{ case (in, v) => when (v) { in.ready := s0_out(idx).ready }}
      }
    }
  }

[test-labeler] make emu error - Exception in thread "main" java.util.NoSuchElementException: NOOP_HOME

Before start
PLEASE MAKE SURE you have done these:

(Select what you have done like this)
I have read the XiangShan Documents.
I just followed the description in the documents.
[x ] I cannot find solutions in the documents.
[ x] I have searched the previous issues and did not find anything relevant.
Describe you problem.
SHA1: OpenXiangShan/XiangShan@a5b77de
CMD: make emu CONFIG=MinimalConfig EMU_THREADS=2 -j8
Error:
Exception in thread "main" java.util.NoSuchElementException: NOOP_HOME at ... () at difftest.DifftestModule$.streamToFile(Difftest.scala:422) at difftest.dpic.DPIC$.collect(DPIC.scala:369) at difftest.gateway.GatewaySink$.collect(Gateway.scala:204) at difftest.gateway.Gateway$.collect(Gateway.scala:121) at difftest.DifftestModule$.finish(Difftest.scala:293) at top.SimTop.$anonfun$difftest$2(SimTop.scala:78) at chisel3.experimental.prefix$.apply(prefix.scala:50) at top.SimTop.$anonfun$difftest$1(SimTop.scala:78) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at top.SimTop.(SimTop.scala:78) at top.SimTop$.$anonfun$new$22(SimTop.scala:109) at freechips.rocketchip.diplomacy.package$.DisableMonitors(package.scala:228) at top.SimTop$.$anonfun$new$21(SimTop.scala:109) at ... () at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace) 1 targets failed xiangshan[chisel3].test.runMain subprocess failed

What did you do before
make verilog --> Succeed!

Environment
Operating System: [e.g. Ubuntu 20.04]
gcc version: gcc (Debian 10.2.1-6) 10.2.1 20210110
mill version: Mill Build Tool version 0.11.1
java version: Java version: 11.0.22, vendor: Debian, runtime: /usr/lib/jvm/java-11-openjdk-amd64
XiangShan branch: master
XiangShan commit id: OpenXiangShan/XiangShan@a5b77de
NEMU commit id: Not applicable
SPIKE commit id: Not applicable

[test-labeler] fuzzy matching

Branch Predcton

[test-labeler] case-sensitive regex matching

ittage

[test-labeler] TLB Timing interface not match with MMIO instruction fetch in IFU

Issue Description:

I have a question about the timing interface for accessing the TLB during MMIO instruction fetches. Although I may not have fully understood the code which is linked in below url. I'm unsure about the behavior of the IFU's (Instruction Fetch Unit) MMIO fetch state machine when checking the TLB's return result.
https://github.com/OpenXiangShan/XiangShan/blob/8fae59bba57fd80fcd1d85aadbf87895b97d167a/src/main/scala/xiangshan/frontend/IFU.scala#L590C1-L590C1

It seems that whenever the condition req.valid && !resp.bits.miss is observed within the same cycle, the state will change. However, the TLB requires at least one cycle to return the correct resp.bits.miss, even though the MMIO TLB is blocking. Suppose a TLB request for a specific MMIO is miss, due to the delayed response by one cycle, the MMIO state machine sees miss == false.B. However, the data in the TLB interface is incorrect.

Personally, I wonder if using resp.valid would be better than resp.bits.miss in this case.

测试

测试中文issue