- design based on lattice reference design for i2c master, adapted based on different requirements.
- rtl design verified by a a testbench implementing a trivial i2c slave. testbench (CoCoTB) comprises a single test case in which a write operation with random data is issued followed by a read operation. it is checked that a master can thus both transmit and receive data correctly.
- $ make
This is a short tabular description of the contents of each folder in the repo.
Folder | Description |
---|---|
rtl | VHDL RTL implementation files |
cocotb_sim | Functional Verification with CoCoTB (Python-based) |
pyuvm_sim | Functional Verification with pyUVM (Python impl. of UVM standard) |
This is the tree view of the strcture of the repo.
. ├── rtl │ └── VHD files ├── cocotb_sim │ ├── Makefile │ └── python files └── pyuvm_sim ├── Makefile └── python files