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a2i

adv_debug_sys

Advanced Debug System

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

another_serv

SERV running Another World under Verilator

axi

AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

axi_mem_if

Simple single-port AXI memory interface

axi_node

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

blabla

Implementation of the BlaBla version of the ChaCha stream cipher

blake2s

Verilog implementation of the 32-bit version of the Blake2 hash function

booth_multipliers

Parameterized Booth Multiplier in Verilog 2001

ca_workshop_munich

Material for the CHIPS Alliance workshop in Munich

caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

caravel-lite

cfu

Proposed RISC-V Composable Custom Extensions Specification (includes Composable Custom Function Unit Specification)

chip_integration_test

clockless-inverter

common_cells

Common SystemVerilog components

core_usb_cdc

Basic USB-CDC device core (Verilog)

cores-swerv

SweRV EH1 core

cores-swerv-el2

corescore

CoreScore

cryptech-cores

Core description files for the Cryptech project

de0_nano

de0_nano_ipxact

docker-images

CI Docker Images

dspfilters

A collection of demonstration digital filters

edalize

An abstraction library for interfacing EDA tools

fewsoc

fifo

Generic FIFO implementation with optional FWFT