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fifo

Generic FIFO implementation with optional FWFT

fossi-foundation.github.io

FOSSi Foundation Website

fpganes

NES in Verilog

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

fusesoc_vunit_demo

Demo project for FuseSoC + VUnit integration

fusesocotb

Quick'n'dirty FuseSoC+cocotb example

gift

Hardware implementation of the GIFT-128 lightweight block cipher

hossein1387.github.io

Personal Website

i2c

I2C controller core

icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

ipxact_gen

ipyxact

Python-based IP-XACT parser

jtag

JTAG Test Access Port (TAP)

jtag_vpi

TCP/IP controlled VPI JTAG Interface.

kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

libaxis

Library of RTL components for AXI Stream infrastructure

libstorage

Library of RTL components for data storage

litedram

Small footprint and configurable DRAM core

migen_uart

It's a UART... written in Migen!

minimax

Minimax: a Compressed-First, Microcoded RISC-V CPU

misato

RISC-V Processor written in Amaranth HDL

mor1kx-generic

mor1kx OpenRISC generic test harness support verilator and iverilog

observer

olofk.github.io

openc910

OpenXuantie - OpenC910 Core

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openlane-examples

Examples from the Openlane repository, adapted as Fusesoc cores

opentitan

OpenTitan: Open source silicon root of trust

or1k-hexloader

OpenRISC Intel Hex bootloader

or1k-ipxact

IP-Xact files for OpenRISC-based systems