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followers: 97.0 following: 87.0 repos: 35.0 gists: 3.0

Name: Omkar Bhilare

Type: User

Company: @BeagleWire @PyFive-RISC-V @SRA-VJTI

Bio: Electronics Enthusiasts. I'm proficient in circuit and PCB designing. I have a great interest in fields like FPGA, Digital VLSI.

Twitter: ombhilare999

Location: mumbai

Blog: https://ombhilare999.github.io

Omkar Bhilare

(Digital Design and Verification Enthusiast)

I'm a final year electronics undergraduate student and I do have great interest in Digital VLSI, FPGA prototyping, RTL Design and verification. In my undergrad I have tinkered a lot with FPGAs, Microcontrollers and circuit designs. I have made my small RISC-V core in verilog. Also made a 8 bit computer using SAP (Simple as possible!) Logic and simulated it in Logisim.
I'm a former verification Research Intern at SHAKTI , RISE LAB, IITM. SHAKTI is an open-source initiative by RISE group at IIT-Madras with the aim to produce production grade processors, complete System on Chips (SoCs), development boards and SHAKTI-based software platform. I was selected in Google Summer of Code 2021 (GSOC'21) with beagleboard org. I had worked on a FPGA cape named BeagleWire and developed Gateware for it.
I'm always open to Research opportunities in Computer Architecture, RTL Design, Verification and FPGA prototyping.

Check my resume for more details: [RESUME]
Check my portfolio site: http://omkarbhilare.me/
Contact me on [email protected]

Omkar Bhilare's Projects

100daysofrtl

100 Days of RTL

8-bit-alu-implementation-on-cyclone-2

Verilog code for 8 Bit ALU and implemented on Intel's Cyclone II

8-bit-computer

8 bit computer using sap logic

aqua_farm_monitor

ESP32 Based IOT system to monitor Aqua Farming

basil

A data acquisition framework in Python and Verilog.

beaglewire

This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/

caravel_user_project

https://caravel-user-project.readthedocs.io

carry-lookahead-adder-cocotb

Verification test of Carry Lookahead Adder using cocotb

dynamatic

gsoc-2021

Log for GSoC 2021: https://ombhilare999.github.io/GSoC-2021/

gsoc-application

gsoc-proposals-archive

This repository contains Accepted proposals for various Google Summer of Code organizations throughout various years!

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

icebreaker-ecp5-examples

Examples for icebreaker ++ board

interconnect-from-scratch-in-chisel

Communication Between two FSMs in chisel

litedram

Small footprint and configurable DRAM core

litex-boards

LiteX boards files

object-avoider-using-ros-and-gazebo

Object Avoider using ROS and Gazebo

ombhilare999

ombhilare999.github.io

https://ombhilare999.github.io/

omni-wheel-bot-in-coppeliasim

pipelinec

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

quantarv

Serial 32bit RISCV Core

riscv-core

A customized RISCV core made using verilog

seven-segment-with-tang-primer-fpga

Seven Segment Interface with Tang Primer

sra-board-2020

SRA development board is a esp32 based board with components on board like motor driver, switches and leds.

sra-board-component

ESP-IDF component for SRA Board

sra-board-hardware-design

ESP32-based Development Board for Robotics and Embedded Applications

sra-vjti.github.io

Repository for SRA Website

tic-tac-toe-

Tic Tac Toe game using C language

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