ombhilare999/interconnect-from-scratch-in-chisel

Communication Between two FSMs in chisel

Omkar Bhilare

(Digital Design and Verification Enthusiast)

I'm a final year electronics undergraduate student and I do have great interest in Digital VLSI, FPGA prototyping, RTL Design and verification. In my undergrad I have tinkered a lot with FPGAs, Microcontrollers and circuit designs. I have made my small RISC-V core in verilog. Also made a 8 bit computer using SAP (Simple as possible!) Logic and simulated it in Logisim.
I'm a former verification Research Intern at SHAKTI , RISE LAB, IITM. SHAKTI is an open-source initiative by RISE group at IIT-Madras with the aim to produce production grade processors, complete System on Chips (SoCs), development boards and SHAKTI-based software platform. I was selected in Google Summer of Code 2021 (GSOC'21) with beagleboard org. I had worked on a FPGA cape named BeagleWire and developed Gateware for it.
I'm always open to Research opportunities in Computer Architecture, RTL Design, Verification and FPGA prototyping.

• Check my resume for more details: [RESUME]
• Check my portfolio site: http://omkarbhilare.me/
• Contact me on [email protected]