openfpga666 Goto Github PK

pyr_down

implement opencv _pyrDown()

python-100-days

Python - 100天从新手到大师

python-mini-projects

A collection of simple python mini projects to enhance your python skills

rcore-tutorial-book-v3

v3.5 https://rcore-os.github.io/rCore-Tutorial-Book-v3/

rembg

Rembg is a tool to remove images background

rtl-design-for-fpga

Engineering Program on RTL Design for FPGA Accelerator

sgbm

implementation of opencv sgbm(disparity map extract) on FPGA

tinylzma

A minimal LZMA data compressor & decompressor. Only hundreds of lines of C.

tinypng-kmeans

效果好于 tinypng.com 的PNG图像压缩器，压缩率&质量可调，摆脱 tinypng.com 的文件数量限制。

tordboyau

A pipelined RISC-V processor

uh-jls

FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。

uniplug-fpga

体积小、低成本、易用、扩展性强的 FPGA 核心板

ustc-rvsoc

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

verilog-fixedpoint

A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

verilog-practice

HDLBits website practices & solutions

verilog-sha-family

Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。

verilog-uart

3 modules: UART receiver, UART transmitter, UART to AXI4 master. 3个模块：UART接收器、UART发送器、UART转AXI4交互式调试器

wavedrom

:ocean: Digital timing diagram rendering engine

xilinx-fpga-pcie-xdma-tutorial

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

xkisp

http://openasic.org/

zedboard-tutorial

Vivado+PetaLinux 系统搭建教程 —— 基于 Zedboard

zfzgit.github.io

zhihu-spider

知乎全站爬虫（用户、话题、提问、回答、评论）以及一些工具，例如知乎搜索，热榜。。。

zynq_cam_isp_demo

基于verilog实现了ISP图像处理IP