Error: dtmcontrol is 0. Check JTAG connectivity/board power.

[athurwo]

Error: dtmcontrol is 0. Check JTAG connectivity/board power.

[MikeOpenHWGroup]

Hi @athurwo, we will need a lot more information to help you out. What is your hardware setup? What are the sequence of commands you invoke?

[gmartin102]

Are you running on a Nexys platform? if so the most common problems are HS2 plugged in the wrong PMOD (it goes on the lower row of JB, and/or switch 0 in the wrong position (near the temp sensor should be towards the board, its connected to TRST)

[athurwo]

Hi @athurwo, we will need a lot more information to help you out. What is your hardware setup? What are the sequence of commands you invoke?

hardware is xilinx K7 FPGA which bitstream downloaded from project core-v-mcu, the command for generate bitstream is make genesys, genesys for K7.
all steps of core-v-mcu-cli-test from README, the final step choice cli_test hs2 to run.
my FPGA board just has one Jtag port. FPGA is xilinx K7.

[athurwo]

Are you running on a Nexys platform? if so the most common problems are HS2 plugged in the wrong PMOD (it goes on the lower row of JB, and/or switch 0 in the wrong position (near the temp sensor should be towards the board, its connected to TRST)

I run on a xilinx K7 FPGA board which just has one JTAG port, others is GPIO.

[athurwo]

my usb cable use FT232H, the run configuer file from project, called openocd-nexys-hs2.cfg, context like below:

adapter driver ftdi
#ftdi_device_desc "Digilent USB Device" # or "Digilent Adapt USB Device"
ftdi_vid_pid 0x0403 0x6014
#ftdi_serial 210249A2FBC2 # change serial, because ZedBoard uses the same chip.
transport select jtag
ftdi_channel 0
ftdi_layout_init 0x00e8 0x60eb

#source openocd-common.cfg
reset_config none

adapter speed 5000
set _CHIPNAME riscv

jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x43651093

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0x0

gdb_report_data_abort enable
gdb_report_register_access_error enable

riscv set_reset_timeout_sec 120
riscv set_command_timeout_sec 120

riscv set_prefer_sba on

scan_chain

init
halt

echo "Ready for Remote Connections"

---

the error is from init this line.

[gmartin102]

I think you misunderstood my comment about the Nexsy board. The only boards supported are the nexsys and genesys boards since the io and pin configuration is crucial to the proper operation of the design. The design implements a JTAG port on FPGA GPIO pins to access the RISCV cpu, Not the Xilinx provided JTAG port. You will need an Digilent HS2 (or equivalent) to connect to the proper IO Pins. To run on the K7 board you will need to rebuild the bitstream for that board.

[athurwo]

I think you misunderstood my comment about the Nexsy board. The only boards supported are the nexsys and genesys boards since the io and pin configuration is crucial to the proper operation of the design. The design implements a JTAG port on FPGA GPIO pins to access the RISCV cpu, Not the Xilinx provided JTAG port. You will need an Digilent HS2 (or equivalent) to connect to the proper IO Pins. To run on the K7 board you will need to rebuild the bitstream for that board.

I mean the jtag port is based on GPIO, the GPIO is special use for jtag. your genensys xilinx chip is same with my k7 fpga chip, that is xc7k325t, so I think my fpga board can use the bitstream generated by "make genesys". now the errors is from jtag.

[athurwo]

Are you running on a Nexys platform? if so the most common problems are HS2 plugged in the wrong PMOD (it goes on the lower row of JB, and/or switch 0 in the wrong position (near the temp sensor should be towards the board, its connected to TRST)

I run on a xilinx K7 FPGA board which just has one JTAG port, others is GPIO.

I think you misunderstood my comment about the Nexsy board. The only boards supported are the nexsys and genesys boards since the io and pin configuration is crucial to the proper operation of the design. The design implements a JTAG port on FPGA GPIO pins to access the RISCV cpu, Not the Xilinx provided JTAG port. You will need an Digilent HS2 (or equivalent) to connect to the proper IO Pins. To run on the K7 board you will need to rebuild the bitstream for that board.

I generated a bitstream which is running water lamp, download to my fpga board by "make downloadg" which is your makefile, result is successful, this mean your makefile and my fpga board, jtag is compatible.

[gmartin102]

Are you running on a Nexys platform? if so the most common problems are HS2 plugged in the wrong PMOD (it goes on the lower row of JB, and/or switch 0 in the wrong position (near the temp sensor should be towards the board, its connected to TRST)

I run on a xilinx K7 FPGA board which just has one JTAG port, others is GPIO.

I think you misunderstood my comment about the Nexsy board. The only boards supported are the nexsys and genesys boards since the io and pin configuration is crucial to the proper operation of the design. The design implements a JTAG port on FPGA GPIO pins to access the RISCV cpu, Not the Xilinx provided JTAG port. You will need an Digilent HS2 (or equivalent) to connect to the proper IO Pins. To run on the K7 board you will need to rebuild the bitstream for that board.

I generated a bitstream which is running water lamp, download to my fpga board by "make downloadg" which is your makefile, result is successful, this mean your makefile and my fpga board, jtag is compatible.

this is from the xdc used to build the genesys bitstream.
set_property -dict { PACKAGE_PIN U27 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[3] }]; #IO_L13P_T2_MRCC_14 Sch=ja_p[1]
set_property -dict { PACKAGE_PIN U28 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[1] }]; #IO_L13N_T2_MRCC_14 Sch=ja_n[1]
set_property -dict { PACKAGE_PIN T26 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[2] }]; #IO_L12P_T1_MRCC_14 Sch=ja_p[2]
set_property -dict { PACKAGE_PIN T27 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[0] }]; #IO_L12N_T1_MRCC_14 Sch=ja_n[2]

the signals Xilinx_io[0:3] are the JTAG pins to communicate with the RISCV, unless your JTAG adapter is connected to those package pins it will not work.

[athurwo]

I think you misunderstand, I mean I can use your genesys configure that include xdc file to generate bitstream, and download to my fpga board successfully, the project core-v-mcu is good, now the problem is the project core-v-mcu-cli-test has some error when download to fpga board, then I cannot validate the the bitstream which had downloaded to my fpga board is good or not.

[gmartin102]

no you cannot use the genesys bitfile on your board unless it is a genesys2 board. even though the pga is the dsame device, the board connectivity is different. the bits stream would need to be regenerated with your board XDC to have the pinout match your board connections.

[athurwo]

no you cannot use the genesys bitfile on your board unless it is a genesys2 board. even though the pga is the dsame device, the board connectivity is different. the bits stream would need to be regenerated with your board XDC to have the pinout match your board connections.

thanks, I am wirting a pin-table file for my fpga board.

[athurwo]

I had modified xilinx_io[3:0] to connect to my board jtag port like below:

set_property -dict { PACKAGE_PIN F10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[3] }];
set_property -dict { PACKAGE_PIN H10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[1] }];
set_property -dict { PACKAGE_PIN G10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[2] }];
set_property -dict { PACKAGE_PIN E10 IOSTANDARD LVCMOS33 } [get_ports { xilinx_io[0] }];
set_property -dict { PACKAGE_PIN AF10 IOSTANDARD DIFF_SSTL15 } [get_ports { sysclk_n }];
set_property -dict { PACKAGE_PIN AE10 IOSTANDARD DIFF_SSTL15 } [get_ports { sysclk_p }];

but still have a error which is :

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 7 out of 50 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: xilinx_io[3], xilinx_io[2], xilinx_io[1], xilinx_io[0], sysclk_n, and sysclk_p.

Why? Where should I modify ?

[gmartin102]

Please look at the emulation directory at the nexsys and genesys2 constraint directories and use the Master XDC file for your specific board to creat a similar structure, then create a pin-table csv file for board and make a new Makefile entry to use the modified files

[athurwo]

Please look at the emulation directory at the nexsys and genesys2 constraint directories and use the Master XDC file for your specific board to creat a similar structure, then create a pin-table csv file for board and make a new Makefile entry to use the modified files

thanks, I try to do.