Comments (1)
Hi @joaopmarinho, thanks for your interest. The format of instructions read by the core on instr_rdata_i
are exactly as defined in the RISC-V ISA. I'd suggest you take a look at the "core" testbench for CV32E40P in the CORE-V-VERIF repo. There is a Quick Start Guide here.
We are not in a position to help you develop your own testbench.
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Related Issues (20)
- Custom Xpulp memory instructions update register file wrongly | Simultaneous port writes
- More undefined conditions for HW loops HOT 3
- Encountered code error when compiling cv32e40p kernel with verilator HOT 23
- Blocking assignment in an always_latch block HOT 7
- Extension 'zicsr' required HOT 3
- Do u guys have any testbenches for modelsim? HOT 2
- Encoding of immediates for PULP SIMD instructions HOT 2
- Non-existent Zicount extension mentioned in introduction HOT 4
- PULP_ZFINX implementation details HOT 2
- Minor error in specification of `cv.insert` and `cv.insertr` instructions HOT 1
- Possible Improvement on Naming of "rd" in Hardware Loop Extension HOT 2
- Implementation HOT 1
- PULP extend instructions encoding in cv32e40p_v1.2.1 User Manual HOT 1
- Does Prefetch Buffer's localparam FIFO_DEPTH and LSU's localparam DEPTH configurable? HOT 2
- Different bahavior between vsim and verilator for mcycle csr HOT 6
- Did Post-Incrementing Load & Store Instructions and Register-Register Load & Store Instructions support misalign load or store HOT 1
- Where is Pulp_Clocking_Gating file? HOT 3
- Is there any physical synthesis performed using 5nm technology for cv32e40p ? HOT 1
- HWLoops lpstart/lpend CSRs 2 LSBs can be written to any value. HOT 1
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