How to flush the data cache?

[Juan-Gg]

How to flush the data cache?

[Juan-Gg]

Issue #410 notes the same problem, and solves it by enabling and disabling the data cache, by writing to the CSR_DCACHE register.

Looking at riscv_pkg.sv, this register is now in 12'h7C1, not in 12'h701 as in the mentioned issue. I have found the following to work for me.

#define FLUSH_D_CACHE() ({__asm__ volatile("csrwi 0x7C1, 0x00"); \
                          __asm__ volatile("csrwi 0x7C1, 0x01");})

[jquevremont]

Have you looked at PMA? This is design-time configuration.

Note that the WT cache is due to evolve to HPDCache.