panda-cores/pandazero

A pipelined, in-order implementation of the RV32I ISA

pandazero's Issues

AUIPC, JALR, JAL not correct

The above instructions only trigger a jump to the respective address, but the flush happens immediately and thus it is no longer propagated to the other stages. As a result, the PC+4 is not stored and return is not possible.

ttest

Execute 10 random programs successful on core

Execute 10 random programs successful on core (to find errors)

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Add wishbone to IF & MEM stages

Make the IF and MEM stages wishbone masters to enable usage of a wishbone interconnect, which in turn enables memory mapped peripherals

upgrade debug module

Common is in progress of changing the debug module, upgrade when done

Create debug module

Write a debug module to enable easier testing than looking at the waveforms

Multiply doesn't work

Investigate whether this is a compiler issue or not

Upgrade Wishbone

common repo has new wishbone interfaces, upgrade time!