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containerization

csrankings

A web app for ranking computer science departments according to their research output in selective venues, and for finding active faculty across a wide range of areas.

difuzz-rtl

digitaljs

Teaching-focused digital circuit simulator

digitaljs_online

Online demonstration for DigitalJS

drawio-desktop

Official electron build of diagrams.net

dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

fpga_as_a_service

fuzzolic

fuzzing + concolic = fuzzolic :)

gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

hammer

HAMMER: Highly Agile Masks Made Effortlessly from RTL

hw-fuzzing

hy220_2022s

hy220_2023s

hy220_2024s

hy425_2021f

hy425_2022f

hy425_2023f

hy523_2022s

hy523_2023s

hy523_2024s

libhugetlbfs

litepcie

Small footprint and configurable PCIe core

nvmecha

NVMe Controller featuring Hardware Acceleration

openocd

OpenOCD python library

papaef.github.io

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

ranc

riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.