patricab/oss-vhdl

oss-vhdl

oss-vhdl
Explore the docs »

Report a Bug · Request a Feature . Ask a Question

---

About

Generic Verilog project template for use with OSS digital design tools

Getting Started

Prerequisites

This project is dependent on the oss-cad-suite by YosysHQ.

Installation

Press the Use this template button on the Github page of this repository.

Usage

This project has the given folder structure. Some features include:

• Cocotb makefile
• Generic modules
  • Pipe module by David Williams

├── modules
│   └── pipe
├── README.md
└── src
    ├── rtl
    └── sim
        └── makefile

Roadmap

See the open issues for a list of proposed features (and known issues).

• Top Feature Requests (Add your votes using the 👍 reaction)
• Top Bugs (Add your votes using the 👍 reaction)
• Newest Bugs

Support

Reach out to the maintainer at one of the following places:

• GitHub issues
• Contact options listed on this GitHub profile

Authors & contributors

The original setup of this repository is by Patric A.B.

For a full list of all authors and contributors, see the contributors page.

License

This project is licensed under the MIT license.

See LICENSE for more information.