pawelperek/eeric-core

Hi, I'm Paweł Perek! 👋

About Me 📚

• 🎓 Bachelor's in Computer Science from AGH University of Technology
• 🌱 Always eager to learn new technologies and programming languages.
• 🎯 Passionate about creating efficient, clean, and maintainable code
• 💻 Contact: [email protected]

🔧 Technical Skills

🛠️ Low-Level Programming

• Languages: Rust, C++, C
• Assembly: RISC-V, ARM, x86, WASM

🌐 Web Development

• Front-end: React, Preact, Rust/Leptos
• Back-end: Rust/Axum, Node.js, Haskell
• Mobile: Flutter, SwiftUI
• DB: PostgreSQL, MongoDB

🧠 Artificial Intelligence

• Basics of FFNN, CNN, RNN with Tensorflow and Pytorch

📂 Projects

• Bachelor's Degree Project on RISC-V (Rust)
• Hospital Automation System (Rust/Axum, NodeJS/Socket.IO, React/MUI)
• Refugee Help App (Dart/Flutter, NodeJS/express&mongo)

eeric-core's Issues

Implement Zfa extension

Although still in 0.1 version, floating point immediate instructions with immediate operands like vli.s and vli.d are perfect for emulator

Implement vector start based on vstart CSR

Stabilize API

Exports of eeric are more or less stable, but before releasing v.0.1 I need to make sure that all structs/enum/traits and whatnot are exported so that projects depending on this library can upgrade to newer eeric version without backwards incompatibilities.

Implement floating point rounding mode based on frm CSR

Use csr[vl] when calculating vector iterator

Current version of the iterator always takes VectorContext::vlmax, so tail elements are processed

Fix grammatical errors in README

ASAP

Regression

Current implementation has very low code coverage and potentially a lot of bugs. After implementation of pre v.0.1.0 issues, all instructions need be tested.

Acceptance criteria:
Vector load/stores: unit tests for SEW::E8, SEW::E16, SEW::E32, SEW::E64
Vector integer instructions: unit tests for SEW::E8, SEW::E16, SEW::E32, SEW::E64
Vector floating point instructions: unit tests for SEW::E16, SEW::E32

VectorContext refactor

Current implementation of vector iterator doesn't take into consideration VL and VSTART CSRs. It would be nice to refactor VectorRegister handle into separate struct

Add shift left by 2 to branch instructions

Refactor VectorEngine out of Core

Since vtype CSR should be the only source of truth for risc-v core, VectorEngine should not be a property of rvcore but a method returned by VectorContext (rename to VectorConfig?)

vlr.v

Instruction vl[nf]re[sew].v must be implemented.
Documentation: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-loadstore-whole-register-instructions

vsetivli

Implement read-only CSR registers

vsetvl

Instruction vsetvl must be implemented.
Documentation: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#sec-vector-config

vsetvli

Instruction vsetvli must be implemented.
Documentation: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#sec-vector-config

vlm.v

Instruction vlm.v must be implemented.
Documentation: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-unit-stride-instructions

Implement B extension

vsm.v

Instruction vsm.v must be implemented.
Documentation: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-unit-stride-instructions