pear0/hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTL4

hdlConvertor

ROADMAP

The System Verilog and VHDL parser, preprocessor and code generator for Python/C++ written in C++. The lower layers are ANTLR4 generated parsers with full language support. Next layer converts this raw Verilog/VHDL AST to simple universal AST (Classes defined in hdlConvertor::hdlObjects and it's python equivalent.). So your project does not not have to care about Verilog/VHDL differences

It is also possible to convert this AST back to original HDL.

This project was extracted from HWT. There is also Java version. But it seems that there is no use for it.

Installation

Use version from this repo as the pip package is currently very old (The pip package will be updated after specified functionality is implemented issues/48.).

Linux:

# note: use up to date compiler, gcc 5.4 is too old
# note that only last 2 are really required rest is downloaded automatically as dependency
sudo apt install build-essential uuid-dev cmake default-jre python3 python3-dev python3-pip libantlr4-runtime-dev antlr4
# note this may be older version than you see in repo
sudo pip3 install hdlConvertor

#or download repository and run
sudo pip3 install -r requirements.txt
sudo python3 setup.py install

Or the same for python 2.7 with other options just for demonstration.

Installer also supports other commands.

# note that setting PYTHONPATH and params after install are there just for example and are not required 
export PYTHONPATH=/tmp/python_install/lib/python2.7/site-packages/
python setup.py install --prefix /tmp/python_install/ -j 8 --build-type Debug -- -DANTLR_JAR_LOCATION=../../../antlr4/antlr-4.7.1-complete.jar -- VERBOSE=1

Other commands:
python setup.py --help-commands

You can also install only C++ library/generate .deb package (nothing specific, just normal cmake-builded library)

mkdir build && cd build
cmake .. && cmake . --build
cpack # to generate .deb package

If you having issues take a look at .travis.yml (build script for the ubuntu 16.04).

Windows:

Take a look at appveyor.yml. It is required to download antlr4 first and have visual studio or other c++ compiler installed.

Also if it is something which is not unique to your system, tell us so we can fix it.

Usage

The HDL AST (the parsed code) is represented by objects from hdlConvertor.hdlAst. In the meantime when there is no wiki yet you can take look at src/hdlAst.py. There are classes for objects in HDL langues and there is also type specified for every properrty.

Example of usage:

import sys
from hdlConvertor.language import Language
from hdlConvertor.toVerilog import ToVerilog
from hdlConvertor import HdlConvertor

c = HdlConvertor()
filenames = ["your.v", ]
include_dirs = []
d = c.parse(filenames, Language.VERILOG, include_dirs, hierarchyOnly=False, debug=True)

tv = ToVerilog(sys.stdout)
tv.print_context(d)

for o in d.objs:
    print(o)

Supported languages:

• VHDL 1076-1993 compatible
• VHDL 1076-2002 compatible
• VHDL 2008, (currently only without tool_directive and PSL) ftp://ftp.lpp.polytechnique.fr/jeandet/keep/sync/vhdl/4772740_IEEE-1076_Standard-VHDL-Language-Ref-Manual.pdf
• Verilog 2001 (based on grammar http://www.syncad.com/VeriLogger_bnf_Syntax_Verilog_2001.htm, https://github.com/antlr/grammars-v4/blob/master/verilog/Verilog2001.g4)
• Currently new universal grammar for System Verilog 2017 and all previous standard is beeing build. The things is WIP as the performance of this implementation is not sufficient for large UVM based projects (you can check speed in travis builds in sv2017 branch).

Similar projects:

(Tell us If you know about some other project!)

• cl-vhdl - lisp, Parser of VHDL into lisp-expressions
• HDL_ANTLR4 - C# projects that use ANTLR4 library to analyse VHDL and Verilog code
• hdlparse - vhdl/verilog parser in python
• ieee1800_2017 - Java, SystemVerilog preprocessor
• pyVHDLParser - python vhdl parser with 2008 support
• rust_hdl - rust vhdl 2008 parser
• slang - Parser and compiler library for SystemVerilog.
• systemc-clang - SystemC Parser using the Clang Front-end
• v2sc - vhdl to systemc
• veelox - Java+ANTLR, An experiment in SystemVerilog Preprocessing
• verilog-parser - A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
• verilog-parser - verilog parser, c
• Verilog-Perl
• vpp.pl - verilog preprocessor with integrated Perl
• sv2v- Haskell, SystemVerilog to Verilog

License

License in top folder applies to this project only. In this repository there are also ANTLR4 grammars (.g4 files - BSD 3, GPL-3, GPL, however they are not present in installation).