poweihuang17 Goto Github PK
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poweihuang17's Projects
gpgpu-sim_distribution
GPGPU-Sim provides a detailed simulation model of a contemporary GPU (such as NVIDIA's Fermi and GT200 architectures) running CUDA and/or OpenCL workloads and now includes an integrated (and validated) energy model, GPUWattch.
home
为推广RISC-V尽些薄力
interface_ft600
An interface for ASIC and FT600
learn_chisel
Learn chisel.
learn_scala_cookbook
Code examples in the book "scala cookbook". It's for me to sharpen my skill about scala and chisel.
leetcode
:pencil: Python / C++ 11 Solutions of LeetCode Questions
linux
My comment and change for Linux kernel source tree
linux-kernel-module-cheat
Run one command, get a QEMU Buildroot BusyBox virtual machine built from source with several minimal Linux kernel 4.14 module development example tutorials with GDB and KGDB step debugging and minimal educational hardware models. Limited GEM5 full system support. "Tested" in x86, ARM and MIPS guests, Ubuntu 17.10 host.
linux-read
Here I would like to record all my understanding of the latest linux, at least for 4.13 rc3
lowrisc-chip
The root repo for lowRISC project and FPGA demos.
make_list
make list for cooking club
open_gpgpu
An open source GPGPU systemverilog project.
openpilot
open source driving agent
opensparc_riscv
porting opensparc t2 to risc-v. Change its front end from sparc to rv64.
orvdebug
An open source BSD-3 implementation of RISC-V debug module.
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
poweihuang17.github.io
My personal website. (Po-wei Huang)
practice_leetcode_and_interview
coding practice for my interview about google or other companies. Mainly about leetcode or other practice.
pulpino
An open-source microcontroller system based on RISC-V
research
dataset and code for 2016 paper "Learning a Driving Simulator"
ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
risc-v-forum-collect
This repo will collect all the threads in risc-v mailing list and I will summarize my findings for each thread.
risc-v-knowledge-collect
This repo will collect all my understanding about risc-v. Including hw, programming guide, and so on.
risc-v-machine-readable-isa
Machine readable ISA for RISC-V
risc-v-qemu-read
Note for my understanding of risc-v qemu
risc-v-verification_framework
Instruction-level verification framework for RISC-V
risc-v_for_newbie
risc-v for newbie
riscv-boom
Berkeley Out-of-Order Machine
riscv-debug-spec
Working Draft of the RISC-V Debug Specification Standard
riscv-fesvr
RISC-V Frontend Server
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