[feature request] adding prefix to coreir/commonlib/... verilog modules

[leonardt]

[feature request] adding prefix to coreir/commonlib/... verilog modules

[rsetaluri]

I think the best option is to have an unsafe output_name field on any CoreIR module (maybe instance too), which will override the default CoreIR name generation logic. Throwing a bunch of logic into name generation @ CoreIR level seems complicated and hard to get right. We could do logic at the higher levels (e.g. magma) to make sure that any output_name overrides are safe.

[leonardt]

A seemingly simple option: provide some option for verilog code generation for a prefix that goes before all modules (e.g. coreir --verilog_module_name_prefix=foo). Then, simply do a pass on all the verilogAST modules and insert the prefix. The main benefit here is that this should work for code that includes multiple namespaces (e.g. we may want to have separate namespaces to handle shared names, but at the end of the day we want everything to have a shared prefix for the above use case). This feels simpler than having to do a pass at the magma level to set output_name for all modules. Also, I'm not sure that would work for commonlib muxes for example, since in magma we reference them as instances of generators, to the actual generated module does not have a handle until rungenerators is invoked later on (so we'd need to do this logic at the coreir level not the magma level)

[rsetaluri]

A code-generation/verilogAST specific pass seems fine to me. I was concerned if it was a CoreIR pass/abstraction, it would be clunky but doing that in verilogAST seems reasonable.

[rdaly525]

The verilogAST pass seems reasonable to me.