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fcad_pcb's Introduction

FreeCAD scripts for PCB CAD/CAM & FEM

fcad_pcb is yet another way to improve ECAD/MCAD collaboration between FreeCAD and KiCAD.

The original purpose of these tools was to do PCB milling in FreeCAD. It can do much more now.:

  • It can generate gcode from kicad_pcb directly without going through the gerber stage.
  • It can let your modify the PCB directly inside FC (done already),
  • and potentially export back to kicad_pcb (partially done).
  • and finally it can generate solid tracks, pads and plated drills to enable FEM and thermal analysis on KiCad pcb boards.

Installation

The fcad_pcb macro is written in Python and requires FreeCAD 0.17 or later to work properly.

  1. Clone this repo into your freecad macro directory. To check what the default path of your macro directory is go to dropdown Macro > Macros.. and find the path in the field User macros location
    cd <path/to/your/macros/directory>
    git clone https://github.com/realthunder/fcad_pcb/
  2. Enter the locally cloned repository
    cd fcad_pcb/
  3. Download the repository submodules
    git submodule update --init --recursive
  4. Restart FreeCAD

Usage

At this time fcad is usable through the FreeCAD python console.

  • Start FreeCAD,
  • Launch the python console Enable through the View > Panels > Python Console dropdown menu
  • Invoke the python import command to load fcad_pcb:
    from fcad_pcb import kicad

Result: you are now ready to use fcad_pcb.

Generating copper layers

from fcad_pcb import kicad
pcb = kicad.KicadFcad(<full_path_to_your_kicad_pcb_file>)
pcb.makeCoppers()

Note: the file path syntax should be one of the following:

pcb = kicad.KicadFcad('C:/Users/fooDesktop/MyProject/MyPCBfilekicad_pcb')

Alternatively if you don't want to replace backslashes for a Windows system:

pcb = kicad.KicadFcad(r'C:\Users\foo\Desktop\MyProject\MyPCBfile.kicad_pcb')`

Generating copper layers / pads / drills + ready for FEM workbench

Generate these full solid objects ready to for the FEM workbench

from fcad_pcb import kicad
pcb = kicad.KicadFcad(<full_path_to_your_kicad_pcb_file>)
pcb.make(copper_thickness=0.035, board_thickness=1.53, combo=False, fuseCoppers=True )
#
# NOTE: KiCAD 5.99 and later added possibility to specify per layer thickness including
#       dielectric layers. You are no longer required to explicitly supply thickness
#       parameters in any of the function calls as shown above.

Supply copper thickness per layer, pass a dictionary instead.

Use either integer or layer name

  • integer (0~31, 0 being the front and 31 the back)

  • layer name for key. Note: key None can be used for default thickness.

    pcb.make(copper_thickness={None:0.05, 0:0.04, 'B.Cu':0.09},
             board_thickness=1.53, combo=False, fuseCoppers=True)
    #
    # NOTE: KiCAD 5.99 and later added possibility to specify per layer thickness
    #       including dielectric layers. You are no longer required to explicitly
    #       supply thickness parameters in any of the function calls as shown above.

Generating a single copper layer

pcb.setLayer('F.Cu')
pcb.makeCopper()

For local nets you have to specify full hierarchical name

pcb.setNetFilter('GND')
pcb.makeCopper()

pcb.setNetFilter('GND','VCC')
pcb.makeCopper()

Shape without intermediate document objects

In case you only want the shape without any intermediate document objects

from fcad_pcb import kicad
pcb = kicad.KicadFcad(<full_path_to_your_kicad_pcb_file>, add_feature=False)

# Or, you can set the parameter later
pcb.add_feature = False

# All the above makeXXX() calls now returns a shape without creating any features
# For example, if you want the complete fused copper layers.
# Note: 'thickness' can be a dictionary for per layer thickness
coppers = pcb.makeCoppers(shape_type='solid', holes=True, fuse=True)
Part.show(coppers)

Note: that there is a sample board to play with inside this repo: test.kicad_pcb

Screenshots

FEM of tracks and drills

Full Board Loaded in FC for FEM

Full PCB in FreeCAD

Full PCB in FreeCAD

PCB for milling

PCB for milling

FEM of tracks and drills

Full Board Loaded in FC for FEM

Requirements

FreeCAD >= v0.17

fcad_pcb's People

Contributors

easyw avatar luzpaz avatar mitjanemec avatar nico-arnold avatar realthunder avatar vagnum08 avatar yrabbit avatar

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fcad_pcb's Issues

Option to import only copper with specific netname

I am currently using your module for DC power analysis using FreeCad FEM solver. I've pretty much got it covered on small test board, but I can see the scalability issue. As the results are needed only for specific nets, it would be great if import would have an option to specify which net to import only. This should significantly reduce the complexity for the mesh and consequently FEM solver.

Or you could import the whole board, but in such a way that specific nets could be modified/deleted.

Boards created from Gerber files in Gerber Viewer

Hi,

for a project we need to import Gerber files and visualize them in 3D. Sadly I'm experiencing problems importing KiCAD-PCB files created from Gerber files in KiCAD Gerber Viewer. I tested this using the following Layout files:
https://github.com/antmicro/alvium-flexible-csi-adapter/tree/master/100mm-single-same-side

You can find the original file (renamed to "Original_project") and the version I exported from the KiCAD Gerber viewer ("Gerber2KICAD_raw" - automatic layer assignment after importing all the Gerber and Excellon files previously exported from the original KiCAD PCB) up here in my cloud:
https://cloudstore.zih.tu-dresden.de/index.php/s/GMygxnZAoinEayS

First problem: FCAD_PCB is missing the "(Setup...)" structure within the KiCAD file. No problem to correct this one by hand or script ("Gerber2KiCAD_corrected". After that all renders fine until the point where pads are created:

16:36:32 Traceback (most recent call last):
File "C:/Users/Nico/AppData/Roaming/FreeCAD/Macro/FreeCAD-OpenEMS-Export-main/FCAD_PCB.FCMacro", line 7, in
pcb.make(copper_thickness=0.035, board_thickness=0.1, combo=False, fuseCoppers=True)
File "C:\Users\Nico\AppData\Roaming\FreeCAD\Macro\fcad_pcb\kicad.py", line 2286, in make
coppers = self.makeCoppers(shape_type='solid',holes=True,prefix=None,
File "C:\Users\Nico\AppData\Roaming\FreeCAD\Macro\fcad_pcb\kicad.py", line 2121, in makeCoppers
copper = self.makeCopper(shape_type,t,fit_arcs=fit_arcs,
File "C:\Users\Nico\AppData\Roaming\FreeCAD\Macro\fcad_pcb\kicad.py", line 2034, in makeCopper
obj = getattr(self,'make{}'.format(name))(fit_arcs=sub_fit_arcs,
File "C:\Users\Nico\AppData\Roaming\FreeCAD\Macro\fcad_pcb\kicad.py", line 1756, in makePads
objs.append(func(vias,'vias'))
File "C:\Users\Nico\AppData\Roaming\FreeCAD\Macro\fcad_pcb\kicad.py", line 1615, in _face
if not cut_wires and not cut_non_closed:
<class 'NameError'>: free variable 'cut_wires' referenced before assignment in enclosing scope

This can be overcome by initializing cut_wires and cut_non_closed variables in the kicad.py around line 1604 or, which is better but still pretty uneglegant, by creating an empty module before the actual structures within the kicad_pcb file. (See file "Gerber2KiCAD_Module")

Still I end up with a PCB covered by tracks but lagging pads and polygons as those are exported as gr_poly or gr_circle no matter if they were a poly or rect or pad - and those don't seem to be drawn. I also managed to get around this by creating seperate modules for the top and bottom copper layer containing the corresponding geometries and replacing every gr_rect with fp_rect, forcing FCAD_PCB into thinking all are footprints. The via and segment geometries still have to stay out of the module. The corresponding file is saved in the cloud as "Gerber2KiCAD_Footprint" - as you can see, this renders nearly everything, but the poly at the bottom isn't fully drawn and an error is shown:

16:56:48 making 4 polys
16:56:50 <Path.Area> Area.cpp(454): ccurve not closed

fcad_pcb_1

fcad_pcb_2

No wonder, as footprints rarely have the complexity as this polygon containing the whole geometry for a cut-out copper zone imported from the raw Gerber data. You can also see the point where everything seems to break down because the polygon line hits a via in its way (see mage attached) and is not drawn further after.

Another way to solve that would be to pack everything into a zone, but I'm curious, is there maybe a way to fix that without the need to apply a patching script like I did here? I would be really happy and thankful for any help. I'll also look into the code again tomorrow to have a try if I can fix that somehow. Still, big ups up for all your work here! With "real" KiCAD files not created externally from Gerber files there are absolutely no problems and it's working like a charm. Same for EAGLE Projects imported into KiCAD.

best wishes from Germany,
Nico

parsing and loading a footprint instead of a board

it is more a desiderata than an issue... 😄
it would be nice to enable fcad_pcb to parsing and loading also a footprint instead of only the board
This is useful to measure and align a 3D model to a footprint (as it is done in ksu, but without the use of fcad_pcb parser which is more flexible and powerful)

no module named fcad_pcb

This might be a really simple problem, but I've been unable to fix it on two Windows PCs and one Ubuntu one. I follow the instructions to clone the repositories and check out the submodules into my macros directory, so I have an fcad_pcb directory inside my macro directory with kicad.py, kicad_parser, etc inside that.

When I try entering "from fcad_pcb import kicad" in the python console in FreeCAD, I get the following error:

Traceback (most recent call last):
File "", line 1, in
File "C:\Program Files\FreeCAD\bin\Lib\site-packages\shiboken2\files.dir\shibokensupport_feature_.py", line 142, in _import
return original_import(name, *args, **kwargs)
ModuleNotFoundError: No module named 'fcad_pcb'

Any ideas?

missing holes at pcb step export in FreeCAD

Hi,
firstly, thanks for your tool. Generally, it is very helpful for me.

My intention is to create a circuit, which is based on pcbs, connected via copper bars.
Therefore, I need a 3d model of the pcbs (made with KiCad) with all its holes (especially vias) and components for use in an external cad tool.

In FreeCAD, I can create the board and copper layers with all the holes by using fcad_pcb and assemble this with the circuit parts.
I export all as step file.
Now, there is the problem. By importing the step file in an external cad tool or back to FreeCAD, some of the holes are not correctly drilled.
Among others, there are only half circle arcs of the holes.

created with fcad_pcb -> all correct
grafik

step-file imported in FreeCAD (board)
grafik

step-file imported in FreeCAD (copper)
grafik

Is this a problem of the fcad_pcb or more of FreeCAD's step export?
Did anyone has this problem as well and possibly a solution?

Thanks and best regards
Thomas

the script does not support the KICAD_CONFIG_HOME enviroment variable

in kicad.getKicadPath() the script assumes the configuration is in the root folder of %APPDATA%/kicad.

But since Kicad V5, you can also have environment variable KICAD_CONFIG_HOME, which can point to a folder within this folder. This makes it possible to have V4 and V5 installations concurrently.

So by default your script uses V4 configuration. As proper step support is available in V5 (in libraries as well as in KiCad) I'd prefer to use V5 configuration by default if both of them exist, but this is an advanced issue, so not many users should be affected, and I patched my version, just thought I should report this.

Cannot install EasyAlias Realthunder Windows 11

I want to get into spreadsheets but I watched a YT video that said I need to install the macro EasyAlias. I am running on Windows 11. I followed his procedure but is says it cannot install it. Also I have no macros showing similar to his. I need some help here please as I am obviously missing something..

PCB Milling in 0.19

I'm unable to find any instruction on how to do milling with your script. I found this in an old forum post :

click 'make path from shape' button in Path workbench to convert to gcode

But this button doesn't exist anymore.
Also, "Create a path pocket" doesn't seems to work as it only supports a single solid. Only part of the board is being milled.
(Freecad 0.19.1, master fcad_pcb)

It's my understanding that milling is the use case of this repository. Maybe it'd be worth adding instructions ?
My goal is to mill tracks with v-bit and drill holes with endmill.

Text support

Is text support planned ? As of latest master and Kicad 5.1, text seems to be ignored.

Milled boards often don't have silkscreen. Text on copper layer is very useful to label connectors, power jacks and such.

makeZones doesn't find a layer in kicad v5.1

Hi @realthunder
here a minimal sample for a board with fill zones that are not built if the pcb is in kicad v5.1 format

The same board saved in kicad v6 format, will build zones.

I'm using these commands:
pcb = kicad.KicadFcad(filename)
pcb.setLayer('F.Cu')
pcb.makeZones(shape_type='face',thickness=0.05, fit_arcs=True,holes=True)

the same issue for layer B.Cu
the warning message is no layers specified
(the same issue if I invoke the command pcb.makeCoppers(holes=True) )
here the two boards:
FillZones-minimal-test-1-kv5.zip
FillZones-minimal-test-1-kv6.zip

py3 compatibility issue

I've tested the tools in
FreeCAD_0.18.14928_Conda_Py3QT5-WinVS2015_x64.7z
and I get the following errors:

Traceback (most recent call last):
File "...../fcad_pcb-test.py", line 22, in
from fcad_pcb import kicad
File ".....\fcad_pcb\kicad.py", line 18, in
from kicad_parser import KicadPCB,SexpList
File ".....\fcad_pcb\kicad_parser_init_.py", line 1, in
from kicad_pcb import *
<class 'ModuleNotFoundError'>: No module named 'kicad_pcb'

pcbnew nightly issue

Recently in kicad 5.99 pcbnew nightly format the 'module' has been changed to 'footprint'
The best would be to keep compatibility for kicad v5 and v6 (5.99 nightly)

kicad v5.1.x

  (module to220-5-horizontal-inverted (layer F.Cu) (tedit 5E344340) (tstamp 5FB81C5D)
    (at 116.84 114.3)
    (descr "TO220HInv, 5pins")

kicad v5.99 (nightly)

  (footprint "to220-5-horizontal-inverted" (layer "F.Cu")
    (tedit 5E344340) (tstamp 00000000-0000-0000-0000-00005fb81c5d)
    (at 116.84 114.3)
    (descr "TO220HInv, 5pins")

I'm attaching a sample board in kicad v5 and v6
test-v6.kicad_pcb.zip
test-v5.kicad_pcb.zip

pcb.makeCopper(fuseCoppers=True) fails with some new pads

Hi,
following our recent conversation I'm uploading some boards with the following pads:

Moreover I'm attaching also a very simple case in which the pcb.make() works, but the pcb.makeCopper(fuseCoppers=True) not
pads-board.zip
pads-drilled-board.zip
(please note that your test.kicad_pcb works just fine, also if saved in kicad v5...
I've not found the solution to this riddle)

Thx in advance
Maurice

Trapezoid pads not yet implemented

Running this against a recent board using trapezoidal pads produces the following error. Otherwise seems to work well.

File "/Users/xyz/Library/Preferences/FreeCAD/fcad_pcb/kicad.py", line 1181, in makePads
    'pad shape {} not implemented\n'.format(shape))
NotImplementedError: pad shape trapezoid not implemented

macro not working on MacOS

Hi real thunder,

I have tried to run your macro on FreeCAD 0.20 on MacOS but was not able.

The macro is installed in the following directory:

/Users/marco/Library/Preferences/FreeCAD/Macro/fcad_pcb

what I do:
I set the working directory to /Users/marco/Library/Preferences/FreeCAD/Macro/fcad_pcb

and then try to run it in the console by writing

from fcad_pcb import kicad

and the result I get is the following:

Traceback (most recent call last):
File "", line 1, in
File "/Users/marco/Library/Preferences/FreeCAD/Macro/fcad_pcb/kicad.py", line 4, in
from future.utils import iteritems
ModuleNotFoundError: No module named 'future'

any suggestion on how to address the problem?

Thanks,

Marco

missing support for Taper footprint

Hi,
would please have a look to this board?
flex-kicad_pcb.zip
The board has taper footprints, built having pad inside a polyline pad (this is done to have DRC and connectivity behavior).
The taper fp is not loaded correctly.
Thanks in advance.

makePads, makeTracks, makeZones fail if no holes in pcb

this is a marginal user case, but using the following commands to create the objects, fcad_pcb is failing:
pcb.makePads(shape_type='face',thickness=0.05,holes=True,fit_arcs=True)
pcb.makeTracks(shape_type='face',fit_arcs=True,thickness=0.05,holes=True
pcb.makeZones(shape_type='face',thickness=0.05, fit_arcs=True,holes=True)

Traceback (most recent call last):
  File "d:fcad_pcb-test-3.py", line 76, in <module>
    pcb.makePads(shape_type='face',thickness=0.05,holes=True,fit_arcs=True)
  File "d:fcad_pcb\kicad.py", line 1662, in makePads
    objs = self._cutHoles(objs,holes,'pads',fit_arcs=fit_arcs)
  File "d:fcad_pcb\kicad.py", line 1503, in _cutHoles
    return self._makeArea(objs,name,op=1,label=label,fit_arcs=fit_arcs)
  File "d:fcad_pcb\kicad.py", line 939, in _makeArea
    ret.Sources = obj
<class 'TypeError'>: type must be 'DocumentObject', list of 'DocumentObject', or NoneType, not list

Antenna-test-design.zip

inconsistent shape of via after applying pcb.via_bound=1

Hi,

after reading #22 I tried the feature via_bound=1 on my model and I've noticed that although all via were filled, not all not all of them were changed to rectangular.

see the picture below
via_problem

Can you please have a look into this? I send you the Kicad file as well

test_V01.zip

As a separate request, when via_bound=1 is used, would it be possible to have a choice on wether you want a circular or square via?

Thanks,

Marco

sexp parser does not support escaped "

related to this ksu issue easyw/kicadStepUpMod#105

If a text field contains an escaped double quote the sexp parser crashed reporting an invalid count of brackets.
For example if a footprint contains:

(fp_text user "Active Area 1.3\"" (at -23 -1) (layer "F.Fab")
  (effects (font (size 0.93472 0.93472) (thickness 0.08128)) (justify left bottom))
  (tstamp 60beab46-be82-4200-a5f9-e65c5b3d7176)
)

kicad v5.99: PCB with a rounded corners

hi,
(recently) kicad v5.99 has switched to write gr_arc as start mid end instead of start end angle

kv5
(gr_arc (start 41.656 73.533) (end 39.878 73.533) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 5C908375))

kv6 (5.99)
(gr_arc (start 41.656 75.311) (mid 40.398764 74.790236) (end 39.878 73.533) (layer "Edge.Cuts") (width 0.05) (tstamp 00000000-0000-0000-0000-00005c908375))

round-corners-kv5.zip
round-corners-kv6.zip

Would it be possible to accept both formats?

Simplify vias

Hi!

Would it be possible to add the option with which vias (hollow cylinder with thin wall) would be substituted with full rectangular object with the same crosssection. Even better would be if crosssection could be controlled.

I am tinkering with FEM simulation of a PCB (thermal and electrostatic) and vias require dense meshing. This simplification would caous significantly less meshing nodes thus reducing FEM calculatio time

KiCAD quoted layer names

Hello
More recent Kicad_pcb files have quoted layer names (i.e. strings, not symbols). The importer doesn't handle that, so it doesn't see elements like (layer "Edge.Cuts").

Here are the old and new files of almost the same board.
pcbs.zip

Add support for oval holes; Add support for blind/micro vias

Hi!

I really appreciate your work done so far. So I humbly ask if you could:

  1. Add support for oval holes
  2. Add support for micro/blind vias

Thanks in advance

I am attaching a test project with the screenshot how the macro behave currently (tested with 5cd7951 on KiCad 5.1.5-90-g5c7ac1bb7(current nightly) an FreeCad 18.4.
Executed code:

from fcad_pcb import kicad
pcb = kicad.KicadFcad("D:/Mitja/Plate/ACS_fcad_pcb_test/ACS_fcad_pcb_test.kicad_pcb")
pcb.make(copper_thickness=0.070, board_thickness=1.32, combo=False, fuseCoppers=True )

KiCad 3D view, board and soldermask not shown:
image
FreeCad 3D view, board hidden:
image

KiCad project
ACS_fcad_pcb_test.zip

loading tracks error on LinkBranch and TNP V1

Hi,
I'm having an issue in loading tracks with FC TN v1 and Link Branch
here the error I get:

19:02:40  making tracks...
19:02:40    making 351 tracks  of width 0.60, (0/2880)
19:02:40  Traceback (most recent call last):
  File "C:/Cad/Progetti_K/3D-FreeCad-tools/fcad_pcb_minimal.py", line 21, in <module>
    pcb.makeTracks(shape_type='face',fit_arcs=True,thickness=0.05,holes=False)
  File "d:fcad_pcb\kicad.py", line 1840, in makeTracks
    objs.append(func(edges,label=label))
  File "d:fcad_pcb\kicad.py", line 1785, in _face
    return _wire(edges,label,True)
  File "d:fcad_pcb\kicad.py", line 1782, in _wire
    return _line(edges,label,width*0.5,fill)
  File "d:fcad_pcb\kicad.py", line 1777, in _line
    wires = findWires(edges)
  File "d:fcad_pcb\kicad.py", line 341, in findWires
    return [Part.Wire(e) for e in Part.sortEdges(edges)]
  File "d:fcad_pcb\kicad.py", line 341, in <listcomp>
    return [Part.Wire(e) for e in Part.sortEdges(edges)]
<class 'Part.OCCError'>: class StdFail_NotDone BRep_API: command not done

and the code I use:

import PySide
from PySide import QtGui, QtCore
import sys,os
sys.path.append(r"d:")
import fcad_pcb
from fcad_pcb import kicad
import importlib
importlib.reload(kicad)
from kicad_parser import KicadPCB
filename= r"D:\Temp\infinitas.kicad_pcb" #"Your-full-path-to-kicad-pcbnew-file"
pcb = kicad.KicadFcad(filename,via_skip_hole=False,via_bound=1)
pcb.setLayer(0) #'F.Cu')
# pcb.makeZones(shape_type='face',thickness=0.05, fit_arcs=True,holes=True)
#coppers = pcb.makeCoppers(shape_type='solid', holes=True, fuse=True)
pcb.makeTracks(shape_type='face',fit_arcs=True,thickness=0.05,holes=False)
# pcb.makeBoard()

and the test file:
infinitas-pcb.zip

Please note this issue is not present on FC main branch (0.20.1 or 0.21)

No module named future.utils

I am getting an error from kicad.py line 4. It says "No module named future.utils"

I cloned the repo to C:\Users\30920\AppData\Roaming\FreeCAD\Macro\fcad_pcb
and checked out the submodules.

Here is my contents of fcad_pcb

.git
kicad_parser
screenshots
tests
.gitignore
.gitmodules
init.py
init.pyc
kicad.py
kicad.pyc
LICENSE
Readme.md

Any help would be appreciated.
Brian

trace not modelled properly while importing to FC

Hi,

although I'm having problems using an updated version of your scripts (see #36) I have tried to run an older working version of your scripts that I have on my laptop and although the script works correctly (checked with your test files) I run into a problem.

You can see the expected trace shown in figure trace_designed_Kicad.jpeg
trace_designed_Kicad

But when I try to import it in FreeCAD and say (in Freecad):
from fcad_pcb import kicad
pcb = kicad.KicadFcad(<FILE_PATH_AND_FILENAME>)
pcb.make(copper_thickness=0.035, board_thickness=12, combo=False, fuseCoppers=True )
I get the result shown in figure trace_problem_during_import_FC.jpeg
trace_problem_during_import_FC

As you can see the traces are all fused in a single copper area. what can be the problem?

Please note that the winding is a pour copper area.

I send you the Kicad project so that you can have all the details of the design.

I hope you can help me with this problem,

Thanks,

Marco

FC_trafo_V01.zip

missing support for (recently added) bspline in pcb Edge-Cuts

It seems that KiCAD has added support for Bspline (not with a direct editing, but importing from an external dxf)
the format is as following:
(gr_curve (pts (xy 126.405224 109.822162) (xy 126.619375 110.505073) (xy 126.940067 111.113882) (xy 127.36623 111.622109)) (layer Edge.Cuts) (width 0.2))
a sample board here:
https://gitlab.com/morganrallen/kickbadge/blob/development/kickbadge.kicad_pcb
coming from this DXF
https://gitlab.com/morganrallen/kickbadge/blob/development/kickstarter.dxf

New freecad user, trying to figure out how to input correctly

Hi,
I am a new user to freecad and I am having trouble with the syntax.
I have a file located at C:\Users\richa\Desktop\ODS Med\Ring_PCB\Ring_PCB.kicad_pcb
I want to import it so I can start milling.

When I type the following I get some error messages below. I am not sure where I messed up.

I am running on Windows 10, 64bit and running Kicad 0.18

from fcad_pcb import kicad
pcb = kicad.KicadFcad(<C:\Users\richa\Desktop\ODS Med\Ring_PCB\Ring_PCB.kicad_pcb>)
pcb.make(copper_thickness=0.035, board_thickness=1.53, combo=False, fuseCoppers=True )

Traceback (most recent call last):
File "C:\Program Files\FreeCAD 0.18\bin\lib\codeop.py", line 168, in call
return _maybe_compile(self.compiler, source, filename, symbol)
File "C:\Program Files\FreeCAD 0.18\bin\lib\codeop.py", line 99, in _maybe_compile
raise err1
File "C:\Program Files\FreeCAD 0.18\bin\lib\codeop.py", line 87, in _maybe_compile
code1 = compiler(source + "\n", filename, symbol)
File "C:\Program Files\FreeCAD 0.18\bin\lib\codeop.py", line 133, in call
codeob = compile(source, filename, symbol, self.flags, 1)
File "", line 1
pcb = kicad.KicadFcad(<C:\Users\richa\Desktop\ODS Med\Ring_PCB\Ring_PCB.kicad_pcb>)
^
SyntaxError: invalid syntax

The above exception was the direct cause of the following exception:

Traceback (most recent call last):
File "C:\Program Files\FreeCAD 0.18\bin\lib\codeop.py", line 168, in call
return _maybe_compile(self.compiler, source, filename, symbol)
File "C:\Program Files\FreeCAD 0.18\bin\lib\codeop.py", line 70, in _maybe_compile
for line in source.split("\n"):
SystemError: <built-in method split of str object at 0x0000021300821670> returned a result with an error set

The above exception was the direct cause of the following exception:

SystemError: <built-in method split of str object at 0x0000021300821530> returned a result with an error set

Error in makeCopper() look like an error creating custom pads

When I try to generate the copper layers of this board
I have this error message:

Traceback (most recent call last):
  File "<input>", line 1, in <module>
  File "mymacropath/fcad_pcb/kicad.py", line 2036, in makeCopper
    obj = getattr(self,'make{}'.format(name))(fit_arcs=sub_fit_arcs,
  File "mymacropath/fcad_pcb/kicad.py", line 1666, in makePads
    w = self._makeCustomPad(p)
  File "mymacropath/fcad_pcb/kicad.py", line 1587, in _makeCustomPad
    wire,width = makePrimitve(key, getattr(params.primitives, key))
  File "mymacropath/fcad_pcb/kicad.py", line 303, in makePrimitve
    width = getattr(params,'width',0)
  File "mymacropath/fcad_pcb/kicad_parser/sexp_parser/sexp_parser.py", line 175, in __getattr__
    return self.__getitem__(name)
  File "mymacropath/fcad_pcb/kicad_parser/sexp_parser/sexp_parser.py", line 146, in __getitem__
    v = self._value[key]
TypeError: list indices must be integers or slices, not str

Command sequence:

>>> from fcad_pcb import kicad
>>> pcb = kicad.KicadFcad("mypcb/hardware/main/main.kicad_pcb")
>>> pcb.makeCopper()

I tried with a simpler board and it works fine

bug when parsing KiCad configuration (on Windows)

Firstly thank you for your work.

Now to the bug report
in fcad_pcb.kicad.getKicadPath() the kicad_common configuration file is opened as binary ("rb").

When running it on FreeCAD_0.18.15221_Conda_Py3QT5-WinVS2015_x64 I get the following error

Traceback (most recent call last):
  File "<input>", line 1, in <module>
  File "C:/Users/MitjaN/AppData/Roaming/FreeCAD/Macro\fcad_pcb\kicad.py", line 340, in __init__
    self.part_path = getKicadPath()
  File "C:/Users/MitjaN/AppData/Roaming/FreeCAD/Macro\fcad_pcb\kicad.py", line 270, in getKicadPath
    match = re.search(r'^\s*KISYS3DMOD\s*=\s*([^\r\n]+)',content,re.MULTILINE)
  File "C:\Programs\FreeCAD_0.18.15221_Conda_Py3QT5-WinVS2015_x64\bin\lib\re.py", line 182, in search
    return _compile(pattern, flags).search(string)
TypeError: cannot use a string pattern on a bytes-like object

changing the line 266 from
with open(kicad_common,'rb') as f:
to
with open(kicad_common,'r') as f:

solved the issue

loading pads for footprint in kicad v6

Kicad has moved from module to footprint in internal syntax
fcad_pcb does support it in loading pads for pcb files, but not for footprints ATM

Would it be possible to accept both formats (kv5 and kv6)?

import PySide
from PySide import QtGui, QtCore
import sys,os
sys.path.append(r"d:")
import fcad_pcb
from fcad_pcb import kicad
import importlib
importlib.reload(kicad)
from kicad_parser import KicadPCB
filename= r"D:\Temp\LED_0603_1608Metric-kv6.kicad_mod"  #SMD kv6
# filename= r"D:\Temp\LED_0603_1608Metric.kicad_mod"  #SMD kv5

pcb = kicad.KicadFcad(filename,via_skip_hole=False,via_bound=0)
pcb.setLayer(0) #'F.Cu')
topP=pcb.makePads(shape_type='face',thickness=0.05,holes=True,fit_arcs=True)

LED_0603_1608Metric.zip
LED_0603_1608Metric-kv6.zip

Trouble with minimum width parameter of polygons

Hi,
I am using your code to extract the copper traces from my pcb's for FEM simulations and so far this works well. But I think I recently found an issue while I was working on a comparatively small pcb. I extracted the copper using:

`from fcad_pcb import kicad

pcb = kicad.KicadFcad(<full_path_to_your_kicad_pcb_file>)

pcb.make(copper_thickness=0.035, board_thickness=1.53, combo=False, fuseCoppers=True )`

but it seems like all my polygons are a little to big. Here is my example pcb in Kicad. The distance between the highlighted polygons is 0.2mm:
Kicad
And here is what I get in FreeCAD using the commands above:
0_2_mm_minimum
As you can see the distance is 0.
I tried some things and I found that the "Minimum Width" Parameter in the polygons settings seems to impact this behaviour (see next picture for the setting).
kicad_polygon_menu
For the test above it was set to 0.2mm. If I reduce it to 0.0254mm for both polygons I get the following result:
0_0254_mm_minimum
The change of "Minimum Width" from 0.2mm to 0.0254mm (which seems to be the minimum in Kicad) meens a difference of approx. 0.17mm, which seems to correlate with the new distance (see picture above).
For me it seems like the parameter "minimum width" is interpreted as some kind of "line thickness" of the polygons outline, which is than "added" to the original polygon.

My Toolchain:
Kicad 6.06
FreeCAD 0.20
latest version of your code

Last but not least: Big thanks for your effort, your code is really useful!

missing feature: Net Tie as tracks

In some RF user case, it is useful to model a footprint partially as Pad ans partially as Net Tie. This will allow to solve DRC issues.

It would be nice to load also *.Cu Net Tie graphic as tacks.

Here a minimal sample file with a polygon:
NetTie-minimal-test.zip
the kicad attribute is fp_poly on Cu layers.

and a sample with fp_line
NetTie-minimal-test-2.zip
the kicad attribute is fp_line on Cu layers.

(it could be also useful as a fp_arc)

Clearence between copper zones distorted

Hello @realthunder

I have been using your macro indirectly through the KiCAD StepUp Workbench, great stuff, thanks a bunch for it!

However, on my latest board I did notice that some zones where fused together and the space between them was not accurate, I raised the issue back at the KiCAD Forums there @easyw recommended me to raise an issue here to see if you could help.

I followed your installation instruction and loaded my board in FreeCAD using directly your plugin and the problem seems to be still there.

KiCAD
image

fcad_pcb
image

The output of the macro looks pretty normal to me:

09:17:00  A3 available
09:19:01  making copper layer F.Cu...
09:19:01    making pads...
09:19:06      modules: 82
09:19:06      pads: 326, skipped: 41
09:19:06      vias: 117, skipped: 0
09:19:06      total pads added: 402
09:19:28    pads done
09:19:28    making tracks...
09:19:28      making 399 tracks  of width 0.20, (0/535)
09:19:32      making 136 tracks  of width 0.60, (399/535)
09:19:38    tracks done
09:19:38    making zones...
09:19:38      making zone /V_SW...
09:19:38        region 1/1, holes: 0
09:19:38      making zone GND...
09:19:38        region 1/2, holes: 0
09:19:38        region 2/2, holes: 0
09:19:38      making zone GND...
09:19:38        region 1/1, holes: 0
09:19:38      making zone /V_SW...
09:19:38        region 1/1, holes: 0
09:19:38      making zone +3V3...
09:19:38        region 1/1, holes: 31
09:19:39      making zone /V_SW...
09:19:39        region 1/1, holes: 0
09:19:39      making zone "Net-(C503-Pad2)"...
09:19:39        region 1/1, holes: 0
09:19:39      making zone /VBAT+...
09:19:39        region 1/1, holes: 0
09:19:39      making zone ""...
09:19:39      making zone "Net-(C206-Pad2)"...
09:19:39        region 1/1, holes: 0
09:19:39      making zone "Net-(L203-Pad1)"...
09:19:39        region 1/1, holes: 0
09:19:39      making zone "Net-(C207-Pad2)"...
09:19:39        region 1/1, holes: 0
09:19:39      making zone "Net-(L204-Pad1)"...
09:19:39        region 1/1, holes: 0
09:19:39      making zone GND...
09:19:39        region 1/1, holes: 0
09:19:40      making zone /V_SW...
09:19:40        region 1/1, holes: 0
09:19:40      making zone "Net-(C205-Pad2)"...
09:19:40        region 1/1, holes: 0
09:19:40      making zone "Net-(C208-Pad2)"...
09:19:40        region 1/1, holes: 4
09:19:40      making zone /V_SW...
09:19:40        region 1/1, holes: 0
09:19:40      making zone "Net-(L201-Pad1)"...
09:19:40        region 1/1, holes: 0
09:19:40      making zone GND...
09:19:40        region 1/1, holes: 0
09:19:40      making zone "Net-(L202-Pad1)"...
09:19:40        region 1/1, holes: 0
09:19:40      making zone "Net-(C205-Pad2)"...
09:19:40        region 1/1, holes: 4
09:19:40      making zone /V_USB...
09:19:40        region 1/1, holes: 0
09:19:40    zones done
09:19:45  done copper layer F.Cu

My FreeCAD version is:

OS: Windows 10 (10.0)
Word size of OS: 64-bit
Word size of FreeCAD: 64-bit
Version: 0.19.23323 (Git)
Build type: Release
Branch: master
Hash: 512d5c6141aec52b6eecc67370336a28fde862a6
Python version: 3.8.6
Qt version: 5.12.5
Coin version: 4.0.0
OCC version: 7.4.0
Locale: German/Germany (de_DE)

Any my KiCAD version is:

Application: Pcbnew
Version: (5.1.8)-1, release build
Libraries:
    wxWidgets 3.0.5
    libcurl/7.71.0 OpenSSL/1.1.1g (Schannel) zlib/1.2.11 brotli/1.0.7 libidn2/2.3.0 libpsl/0.21.0 (+libidn2/2.3.0) libssh2/1.9.0 nghttp2/1.41.0
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
    wxWidgets: 3.0.5 (wchar_t,wx containers,compatible with 2.8)
    Boost: 1.73.0
    OpenCASCADE Community Edition: 6.9.1
    Curl: 7.71.0
    Compiler: GCC 10.2.0 with C++ ABI 1014

Build settings:
    USE_WX_GRAPHICS_CONTEXT=OFF
    USE_WX_OVERLAY=OFF
    KICAD_SCRIPTING=ON
    KICAD_SCRIPTING_MODULES=ON
    KICAD_SCRIPTING_PYTHON3=OFF
    KICAD_SCRIPTING_WXPYTHON=ON
    KICAD_SCRIPTING_WXPYTHON_PHOENIX=OFF
    KICAD_SCRIPTING_ACTION_MENU=ON
    BUILD_GITHUB_PLUGIN=ON
    KICAD_USE_OCE=ON
    KICAD_USE_OCC=OFF
    KICAD_SPICE=ON

Let me know if I can somehow assist you further and once again, thank you for your time and effort!

P.S. I haven't been able to reproduce the problem with a test board, as such here is the original board with the problem:
charger.zip

How to create a drilling operation easily?

Hello,
I have a naive question. I have a Kicad file with a board that contains about 130 holes. I know that one can auto create Path Drilling Object in Path WB from features of a job base object.

If I create a job with a board_solid # F.Cu as the base object, then the holes are not found automatically.
I can add each hole with the mouse, but I'm afraid of making a mistake and skipping something.

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