Support vxrm intrinsics

[riscv-non-isa]

Support vxrm intrinsics

[ebahapo]

Rather, shouldn't a library that supported RVV set vxrm as part of supporting fenv.h instead?

[zakk0610]

We had purposed vread_csr and vwrite_csr interface here, but it is not included in intrinsic RFC and function list yet

enum RVV_CSR {
  RVV_VSTART = 0,
  RVV_VXSAT,
  RVV_VXRM,
  RVV_VCSR,
};

unsigned long vread_csr(enum RVV_CSR csr);
void vwrite_csr(enum RVV_CSR csr, unsigned long value);

Any comments or suggestions will be appreciated.

[arcbbb]

I prefer HK's idea having specific API to read/set vector rounding mode.
In that way user doesn't need to know the format of CSR in order to read the content.

[kito-cheng]

I prefer high-level API for that too, the only concern to me is it's not intrinsic.

[HanKuanChen]

@kito-cheng do you think this is a semantic intrinsic?
If so, I think we should add this.

[HanKuanChen]

I propose a new pull request #46 and a simple implementation here.

#define VE_TONEARESTUP 0
#define VE_TONEARESTEVEN 1
#define VE_DOWNWARD 2
#define VE_TOODD 3
// Each of these macro constants expands to a nonnegative integer constant expression.

// return 0 on success, non-zero otherwise.
int vesetxround(int round)
{
	switch(round)
	{
	case VE_TONEARESTUP:
	case VE_TONEARESTEVEN:
	case VE_DOWNWARD:
	case VE_TOODD:
		asm volatile("csrw vxrm,%z0"::"rJ"(round));
		return 0;
	default:
		return -1;
	}
}

// return the current rounding macro, negative value if the rounding mode cannot be determined.
int vegetxround(void)
{
	int vxrm;
	asm volatile("csrr %0,vxrm":"=r"(vxrm));
	switch(vxrm)
	{
	case VE_TONEARESTUP:
	case VE_TONEARESTEVEN:
	case VE_DOWNWARD:
	case VE_TOODD:
		return vxrm;
	default:
		return -1;
	}
}

// clear vxsat
inline void veclearxsat(void)
{
	asm volatile("csrw vxsat,x0");
}

// return 1 if vxsat is set, 0 otherwise.
inline int vetestxsat(void)
{
	int vxsat;
	asm volatile("csrr %0,vxsat":"=r"(vxsat));
	return vxsat;
}

[kito-cheng]

We define vxrm and vxsat as call clobber in psABI, so this proposal become impossible to implement now.

[1] riscv-non-isa/riscv-elf-psabi-doc#294