riscveval Goto Github PK

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

controlpath-datapath-asmd-designtosynthesiswithskywater130

This repository highlghts the basic design of manual datapath and control path with ASMD Chart and its comparison with the synthesis from behavior level RTL and finally the synthesised design is mapped to the Skywater130nm standard cells and Netlist is generated

flight-controller-design-for-shakthi-c64-processor

This is a SIMULINK based Control System Design for a Quadcopter. The Control System was designed in SIMULINK and the Embedded C Code and Verilog code were generated using SIMULINK Coder. This was aimed at developing a flight controller using the RISCV ISA based SHAKTHI-C64-Vajra Microprocessor developed at RISE Labs, IIT Madras, India

hf-risc

implementation-of-error-detection-codes-in-python

implementation-of-line-encoding-schemes-in-python

lowrisc-chip

multisim-simulations-and-spice-files-analog-electronic-circuits

This is my collection of Multisim Simulations for the classic analog electronic circuits ranging from rectifiers, oscillators, voltage regulators , Astable, Bistable , Monostable Multivibrators.

orca

orca-1

RISC-V by VectorBlox

physical-design-with-openlane-using-sky130-pdk

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified

picorv32

potato

pulpino

pulpino-zedboard-images

qunetsim

A quantum network simulation framework.

ri5cy-gnu-toolchain

ridecore

riscv-tools

rocket-chip

sequential-binary-multiplier---design-and-synthesis-with-skywater-pdk

This repository highlights the design procedure of a simple sequential binary multiplier manually using ASMD Charts and its RTL implementation in verilog and synthesis using Skywater130nm pdk. Refer Concept.pdf to look at the design steps

sifive_freedom

sifive_freedom_e_sdk

vscale

vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

zephyr-riscv