Any crack in a structure changes the strain profile of the material underneath. In situations like a boiler or a jet engine this can be critical. This strain can be detected using a strain gauge i.e. a device which changes its electrical resistance which change in strain. So if such a variable resistor is placed in a voltage divider/wheatstone bridge we can get different voltage levels for different strains detected. This change in voltage can be sensed by a Mixed signal SoC as discussed in this design.
- The Implementation Overview
- PIPO (parallel in parallel out)
- Priority Encoder
- Verilog codes for designing digital blocks
- Complete crack sensing Circuit and Simulation results
- Layout of the CSC Circuit
- Acknowledgments
- References
This circuit is implemented using the following 5 stages:-
- The voltage divider (for the sake of this simulation, the voltage is directly taken)
- 3-bit Flash type ADC to convert that voltage level into digital output
- A 8x3 priority encoder to convert the ADC output to binary code
- A PIPO to send data from the encoder to lcd every clock cycle
- LCD interfacing circuit to display the data on a LCD
Also called the parallel A/D converter, this circuit is the simplest to understand. It is formed of a series of comparators, each one comparing the input signal to a unique reference voltage. The comparator outputs connect to the inputs of a priority encoder circuit, which then produces a binary output. The following figure shows a 3-bit flash ADC circuit:
Vref is a stable reference voltage provided by a precision voltage regulator as part of the converter circuit, not shown in the schematic. As the analog input voltage exceeds the reference voltage at each comparator, the comparator outputs will sequentially saturate to a high state. The priority encoder generates a binary number based on the highest-order active input, ignoring all other active inputs.
The calculation for eg. an input of 0.8 V with Vref = 1.1 V:
The input lies in the range (these voltages can be found by voltage divider calculations) 5/8 * Vref and 6/8 * Vref which would make the output of the 5th comparator high which would give the corresponding input to priority encoder which would give the output 101 (5).
comparator circuit compares two voltages and outputs either a 1 (the voltage at the plus side) or a 0 (the voltage at the negative side) to indicate which is larger. Comparators are often used, for example, to check whether an input has reached some predetermined value.
Flash analog to digital converter is the fastest type of ADC among all the other ADCs. It is also known as a parallel analog to digital converter. It comprises high-speed comparators, resistive voltage divider circuits along with a priority encoder.
An N-bit flash ADC consists of 2 powered N-1 comparators and contains 2 powered N number of matched resistors.
Parallel In Parallel Out (PIPO) shift registers are the type of storage devices in which both data loading as well as data retrieval processes occur in parallel mode. A shift register is one type of sequential logic circuit where its output mainly depends on its input & previous output. This register includes a set of Flip Flops where these are connected within cascade which means, one FF output is simply connected to the input of another FF. This register is used to store as well as shift the group of binary data. The number of FFs available within the shift register mainly depends on the no. of binary bits stored within the register. Here we are implementing a 3 bit PIPO.
The LCD interfacing circuit is a circuit designed in verilog to transfer the input on its terminal to a LCD (16x2 as shown in the figure) on every register select operation.
A D (or Delay) Flip Flop (Figure 1) is a digital electronic circuit used to delay the change of state of its output signal (Q) until the next rising edge of a clock timing input signal occurs. Since the output remains constant unless deliberately changed by altering the state of the D input followed by a rising clock signal.
A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the index of the most significant activated line, starting from zero. They are often used to control interrupt requests by acting on the highest priority interrupt input.
1)Priority Encoder
module krunal_priority(i,d);
// declare
input [7:0] i;
// store and declare output values
output [2:0] d;
reg [2:0] y;
always @(i)
begin
// priority encoder
// if condition to chose
// output based on priority.
if(i[7]==1) y=3'b111;
else if(i[6]==1) y=3'b110;
else if(i[5]==1) y=3'b101;
else if(i[4]==1) y=3'b100;
else if(i[3]==1) y=3'b011;
else if(i[2]==1) y=3'b010;
else if(i[1]==1) y=3'b001;
else
y=3'b000;
end
assign d = y;
endmodule
- PIPO register
module krunal_pipo(clk,a,q);
input clk;
input[2:0]a;
output[2:0]q;
reg[2:0]q;
always@(posedge clk)
begin
q<=a;
end
endmodule
- LCD interfacing circuit
module lcd_2(
clk,
din,din1,din2,
output reg rs, rw,
output reg dout
);
input reg clk;
input din;
input din1;
input din2;
integer i = 0;
reg [2:0] data = 0 ;
always@(posedge clk)
begin
data[0] <= din;
data[1] <= din1;
data[2] <= din2;
if(i <= 2)
begin
rs <= 1'b1;
rw <= 1'b0;
dout <= data[i];
i <= i + 1;
end
else
begin
i <= 0;
rs <= 1'b0;
rw <= 1'b0;
dout <= 1'b0;
end
end
endmodule
This circuit consists of FLASH ADC, made through comparators and resistors, including a 8:3 priority encoder and a PIPO circuit(made using 3 D flip-flops).
This area is in µm^2.
- Post Layout Simulations needs to be performed.
- Output Waveforms of Post Layout Simulation with Post Schematic Waveforms needs to be match.
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
- Madhav Rao, Associate Professor, IIIT Bangalore
- Kavya Agarwal, Mtech ECE student, International Institute of Information Technology, Bangalore
# Contact Information
- Ritesh Lalwani, Mtech ECE student, International Institute of Information Technology, Bangalore [email protected]
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. [email protected]
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