Why Tensor's have this exact size?

[Bbllaaddee]

Why Tensor's have this exact size?

[romeric]

Yes this is expected. It is due to SIMD vectorisation. If you want the tensors to have the expected sizes you can use the pragma FASTOR_DONT_VECTORISE. If your system is so constrained (stack-size wise) then this is the only way to get around that. You will still have access to all features of Fastor.

Scaling up the tensors to such sizes is extremely cache friendly as the data can be packed nicely into the CPU vector register once loaded (in case it is not already loaded) and masking the upper part of the registers can be avoided.

[J-S-Robinson]

Maybe to ensure 16-bit alignment?

If not, I'd guess it is for SIMD optimization. If the padded parts of the SSE or AVX vector are stored in memory as zeros, you can skip setting the padded values to zero?