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Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)

License: MIT License

Python 100.00%
testbench-generator verilog-a verilog-ams waveform-generator cadence cadence-virtuoso generator simulation veriloga testbench

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vagen's Issues

Using functions in sequence

Hi,

I like this module a lot, I am using it a lot. But I have a question which popped up when I was writing the sequence a little bit more structured. Maybe (I hope so) it's just a question of the syntax.

How to write it, when I would like to "call a function" in the sequence, e.g. a modification of the example from the README:

def firstSeq():
    VDD.setRiseFall(10e-6, 10e-6),
    VDD.applyV(5.0),
    va.WaitUs(10), 
    CLK.on(4e6),
    va.WaitUs(1),

#Sequence
mod.seq(True)(
    firstSeq(),
    RST.write(True),
    va.WaitSignal(EVNT_READY),
    OUT.setRiseFall(100e-9, 100e-9),
    OUT.applyI(100e-3), #Positive current enters the model
    va.WaitUs(10),

```    CONFIG_VOUT.write(5),
    va.WaitUs(20),
    va.Finish()
)

Many thanks for the module and all your support!
KR,
Christof

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