rrotaru/cs385-cpu

CPU designed in Verilog

Hello. I'm Rob. 👋

This is my GitHub README. I will try to keep helpful and interesting things here.

About me

I enjoy the extremes of being either hyper-connected to everything tech/digital or completely disconnected and out in the woods. I'm an avid backpacker, a keyboard enthusiast who dabbles in DIY projects, and a novice guitarist. I enjoy everything of the synthwave/cyberpunk variety. I completed undergrad with a Bachelor of Science degree in Mathematics and a Bachelor of Science degree in Computer Science from CCSU.

I am a software engineer who works with automation tools for deployment and configuration of enterprise-scale systems.

Long but interesting reads

1. WaitButWhy's Neuralink post
2. You Don't Know Javascript

Helpful Documentation...

Git

1. Atlassian's Git Tutorial - Getting Started
2. Understanding Git Conceptually
3. Conventional Commits - a specification for adding human and machine readable meaning to commit messages
4. Conventional Comments - comments that are easy to grok and grep
5. Markdown Architectural Decision Records - a solution to record architectural decisions

AWS

1. AWS Solutions Architect Notes

Software Development

1. The Missing Semester of Your CS Education
2. Learn X in Y Minutes

JavaScript

1. JavaScript.com

cs385-cpu's Issues

CPU module not working.

Test output for the CPU modules gives us a lot of "don't care" values (x's) where we should be getting output. Traced this down to a problem in either regfile or something to do with the register file modules, where we are getting don't cares for A and RD2 on line 104 of MIPS-CPU.vl

    reg_file rf (IR[11:10], IR[9:8], WR, AluOut, RegWrite, A, RD2, clock);

when we should be getting real values.

Anyone else let me know if you can get to the bottom of this. I'm trying to work on it but I don't think I understand the register file enough to make progress.