rsnikhil Goto Github PK
Name: Rishiyur S. Nikhil
Type: User
Company: Bluespec, Inc.
Bio: Hardware design: mostly RISC-V, mostly using Bluespec BSV. Also Haskell, RISC-V Formal Specifications, tutorials.
Location: Framingham, MA, USA
Name: Rishiyur S. Nikhil
Type: User
Company: Bluespec, Inc.
Bio: Hardware design: mostly RISC-V, mostly using Bluespec BSV. Also Haskell, RISC-V Formal Specifications, tutorials.
Location: Framingham, MA, USA
Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
Bluespec BSV HLHDL tutorial
Book to (1) learn BLang (BSV) using a RISC-V example and (2) learn to design a pipelined RISC-V CPU using BSV for HDL coding
Bluespec Compiler (BSC)
Economical/Elementary Debugger
Modeling the WW2 Enigma crypto machine in Cryptol and Bluespec BSV
An experimental DSL to describe the full feature list of a RISC-V implementation, along with constraints on features and between features
Formal specification of RISC-V Instruction Set
A standalone parser for BSV (Bluespec SystemVerilog) written in Go
Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
Miscellaneous Utilities
Slides from Multithreaded Architectures tutorial 1993 by Rishiyur S. Nikhil
A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
Sail RISC-V model
Temporary work site for another project (please ignore until public announcement)
An AWS-FPGA Testbed for Architecture Research on RISC-V CPUs, Accelerators, and Memory Systems
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