Department of Electrical & Electronic Engineering
Imperial College London
Originally created by Prof. Peter Cheung and Prof. Christos Bouganis, now renovated by Dr. Aaron Zhao ([email protected]) and Sarim Baig, and reviewed and tested by Cheng Zhang.
The aim of the module is to enable students to design information processing systems of medium complexity, by considering communication and computation costs, as well as local (embedded) and server-side processing. The module builds upon the materail you have been taught in your EIE year two, and introduces the practical aspects of embedded processing, networking, and databases. The first part of the module consists of a series of practical labs where you will be exposed to the practical aspects of embedded processing, networking and datasets, followed by a practical component (i.e. coursework) with strong emphasis on the design methodolody, where a fully operational processing system needs to be designed.
Upon successful completion of this module, you will be able to:
- Develop an embedded system based on a CPU/FPGA
- Apply signal processing. techniques to a time-series data considering their computational cost
- Develop the communiction infrastructure between a local node and a server
- Design a database that communicates with the rest of the system
- Judge the compute capabilities of different platform
In this module the principles and techniques for designing information processing system will be studied. The module covers the following topics:
- Introduction to Field Programmable Gate Arrays (FPGA)
- Introduction to the design process of a digital system using an FPGA
- Soft core CPU (NIOSII) architecture
- Interfacing a CPU with external peripherals
- UART and SPI interfaces
- Establishing a communication with a AWS server
- Instantiate a database on a remote server
If you meet any problems, one should either create an issue or send an email to Dr. Aaron Zhao ([email protected])
Quick pointers to all labs.
- Lab 1 - Introduction to DE10-Lite and Setting up Quartus Prime Lite
- Lab 2 - Design a NIOS2 System
- Lab 3 – Integrate an accelerometer with a NIOS
- Lab 4 - Integrate an accelerometer with a NIOS
- Lab 5 – AWS, SSH Clients, Client Server Programming (By Sarim)
- Lab 6 – Using DynamoDB with EC2, Python based (By Sarim)
Useful links (Imperial Account Required)
- Resources: more on DE10, QSys, etc..
- Overall Course Arrangement and Team Allocation
- Midterm Assessment Information
- Quartus and Eclipse environment (From Christos, complements to lab1)
- Programming environment setup (From Christos, complements to lab1)
- Team making proposals
- Past Projects
| Week Number | Date | Lab Name | Lab Time |
|---|---|---|---|
| 2 | 18th Jan (Thu) | Group B lab | 9am-11am |
| 3 | 23th Jan (Tue) | Group A lab | 4pm-6pm |
| 3 | 25th Jan (Thu) | Group B lab | 9am-11am |
| 4 | 30th Jan (Tue) | Group A lab | 4pm-6pm |
| 4 | 1st Feb (Thu) | Group B lab | 9am-11am |
| 5 | 6th Feb (Tue) | Group A lab | 4pm-6pm |
| 5 | 8th Feb (Thu) | Group B lab | 9am-11am |
| 6 | 14th Fen (Wed) | Lab Oral | 10am-12am |
| 7 | 20th Feb (Tue) | Group A lab | 4pm-6pm |
| 7 | 22nd Feb (Thu) | Group B lab | 9am-11am |
| 8 | 27th Feb (Tue) | Group A lab | 4pm-6pm |
| 8 | 29nd Feb (Thu) | Group B lab | 9am-11am |
| 8 | 5th Mar (Tue) | Group A lab | 4pm-6pm |
| 8 | 7th Mar (Thu) | Group B lab | 9am-11am |
| 9 | 12th Mar (Tue) | Group A lab | 4pm-6pm |
| 9 | 14th Mar (Thu) | Group B lab | 9am-11am |
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