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adaptive-median-filter-in-verilog

Implementation of an Adaptive Median Filter in Verilog (Simulation only)

arty_s7_playground

Digilent's Arty S7-50 in Verilog 2001

axi4_lib

AXI4 Interface Library

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

corundum

Open source FPGA-based NIC and platform for in-network compute

darknet

Convolutional Neural Networks

ddr3-controller

A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

ddr3_controller

digilent-xdc

A collection of Master XDC files for Digilent FPGA and Zynq boards.

dual_port_ram

fifo_lib

fixedpoint

Library for fixed point arithmetic in C++

gigevision-xilinx

GigE Vision compatibe video streaming from MIPI-CSI camera with Zybo Z7-10 board

h264

H264视频解码verilog实现

hw

RTL, Cmodel, and testbench for NVDLA

iperf

iperf3: A TCP, UDP, and SCTP network bandwidth measurement tool

keepoutlookrunning

Little add-on to keep outlook running when clicking on exit

kvazaar

An open-source HEVC encoder

linux-digilent

Linux Repository for digilent boards

mmap

Sample mmap code (utilizing kmalloc pages as "backing device")

nat-1

A Linux kernel module that does network address translation

netfilter-full-cone-nat

A kernel module to turn MASQUERADE into full cone SNAT

netfpga

NetFPGA 1G infrastructure and gateware

netfpga-10g

Yilong's NetFPGA-10G Repo

openh264

Open Source H.264 Codec

openisp

Image Signal Processor

pciutils

The PCI Utilities

progasicp4switch

progASICp4SWITCH

seali-rgb

Config files for my GitHub profile.

swerv-iss

Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator