- ๐ Hi, Iโm @seali-rgb
- ๐ Iโm interested in FPGA/digital design/embedded systems.
- ๐ฑ Iโm currently an fpga isp engineer
- ๐๏ธ Iโm looking to collaborate on networking/image processing
- ๐ซ How to reach me: [email protected]
seali-rgb / adaptive-median-filter-in-verilog Goto Github PK
View Code? Open in Web Editor NEWThis project forked from rbahrami/adaptive-median-filter-in-verilog
Implementation of an Adaptive Median Filter in Verilog (Simulation only)
License: MIT License