shetaye / omega-cpu Goto Github PK
View Code? Open in Web Editor NEWA 32-bit RISC CPU written in VHDL
License: GNU Lesser General Public License v3.0
A 32-bit RISC CPU written in VHDL
License: GNU Lesser General Public License v3.0
In the operations that write to register 30 as a status register (carry bit), if register 30 is also designated as the operation's "output" register, it is unclear what value actually gets written.
This should be clarified, probably by removing the ability to write to register 30 as a general-purpose register.
Currently, the assembler produces its machine-code output in lines of binary originally intended for a GHDL test bench. A post-process script exists to convert it to VHDL array format. There is no provision for straight binary output.
The assembler itself should support these three output formats, as it was originally designed. This can be done by adding new visitor classes alongside TextOutputVisitor
and adding a command-line switch to choose among them when the finalOutput
function is called:
https://github.com/Hyperion302/omega-cpu/blob/e6e8a70d20045856365634b33294ff635fceb88d/Assembler/OmegaAssembler.py#L963
Any instruction whose upper 6 bits are 110111 is treated as a NOP. These should raise an "invalid instruction" trap instead.
It is unclear what happens when the processor encounters an instruction with the "reserved" opcode 111. This should be clarified and an "invalid instruction" trap raised on such an instruction.
Currently, whenever an interrupt is triggered and serviced, the return address is supposed to be written to register 29.
However, register 29 is also usable as a general-purpose register and is designated by the calling convention as holding the return address from ordinary functions. This will cause a problem whenever an interrupt is serviced in the middle of a function call, wiping out the return address.
The .data
directive in the assembler is designed to support an address operand indicating where to put the segment, the same as the .text
directive does. However, the assembler raises an error when an address is provided.
The divide-immediate instruction (DIVI
), like its register counterpart, uses the least significant bit of its instruction as the "divide mode" bit to select between signed and unsigned mode.
However, this bit is also part of the immediate value, so any division by an even number is done in unsigned mode and any division by an odd number in signed mode.
To resolve this, DIVI
must ignore the DM bit and operate exclusively in one mode or the other.
The documentation currently designates it as operating in signed mode.
When segment addresses are explicitly specified in the assembler, there may potentially be two or more instructions assigned to the same memory address (if, for example, two segments are given the same address).
Currently, the assembler handles this by the deterministic, but potentially confusing route of silently disambiguating in favor of the last instruction or directive, in document order. It might improve usability if the assembler alerted the user to any overlap.
It is possible to assign a value to the program counter that is not a multiple of 4, whether by outputting directly to register 31, or by using a register-mode jump instruction. Since instructions are always at word-aligned addresses (multiples of 4), this would cause some highly unexpected behavior.
This should be prevented by fixing the lower two bits of the PC permanently at zero.
When performing a multiplication, the ALU outputs the upper 32 bits of the product to the "register D" output, but this value goes unused by the controller. The R[D]
field should be added to the multiply instruction to provide an outlet for this value.
The instructions SLLV,
SLL, and
EQ` are usable with two different opcodes, as shown in Table 6 of the documentation. The duplicate opcodes, which the assembler does not use, should raise an "invalid instruction" trap instead.
The label names in the functions in the lib
directory are of a sort that could be easily used in a user program (e.g., end
), which is a problem since these labels are in a global namespace and hence have to be globally unique.
This problem could be alleviated by mangling the names to something much less likely to be used in a user program (e.g., print_string__end
).
Currently, although trap events such as divide overflow are raised within the processor, their handlers are no-ops and the program has no way of knowing that an error occurred. Eventually, these should be handled as interrupts.
A declarative, efficient, and flexible JavaScript library for building user interfaces.
๐ Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
The Web framework for perfectionists with deadlines.
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. ๐๐๐
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
We are working to build community through open source technology. NB: members must have two-factor auth.
Open source projects and samples from Microsoft.
Google โค๏ธ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.