shinkuan/icc2012_b

IC Contest 2012 B

2012 IC Design Contest Preliminary
標準元件數位電路設計 – 大學/研究所組
NAND Flash Memory Controller

Explore the docs »

Report Bug . Request Feature

Table Of Contents

• Table Of Contents
• About The Project
  • 問題描述
• Usage
  • Basic usage
  • Locking the circuit
  • Wartermark
  • TMR
• TODO
• License
• Authors

About The Project

問題描述

　　請完成一快閃記憶體控制(NAND Flash Memory Control)電路設計。此控制電路的功能是將快閃記憶體 A 的資料完全複製至快閃記憶體 B。
　　本控制電路有 4 只信號輸入(clk, rst, F_RB_A, F_RB_B)、9 只信號輸出(done,F_CLE_A, F_ALE_A, F_REN_A, F_WEN_A, F_CLE_B, F_ALE_B, F_REN_B, F_WEN_B)及 2 只記憶體雙向輸出入信號(F_IO_A, F_IO_B)，如圖 一所示，關於各輸入/輸出信號的功能說明，請參考表一。
　　本試題有使用到快閃記憶體模型(flash simulation model)，其中內含時序檢查，若要避免 RTL模擬時所産生的時序檢查錯誤(setup or hold violation)，可參考附錄 B 的第 4 點來進行模擬。
　　每個參賽隊伍必須根據下一節所給的設計規格完成計。參賽隊伍可藉由 CIC 所提供的輸入指令及正確結果檔來檢查設計是否有達到要求，詳情請參考附錄 B。

Usage

Basic usage

1. cd into B_ICC2012_preliminary_all_cell
   • cd ./B_ICC2012_preliminary_all_cell/
2. use ncverilog to run testbench. You may choose p1 or p2. +FSDB to generate fsdb file.
   • ncverilog testfixture.v NFC_ORIG.v +define+p1+FSDB +access+r
3. You can use load.tcl to load NFC.v into Design Vision.
4. Load timing constrain for Flash using set_timeviolation.tcl
5. Provided a simple way to report and save result using ReportAndSave.tcl
6. After synthesis, run post-syn simulation using:
   • ncverilog testfixture.v ./Report/NFC_syn.v +define+p2+FSDB+SDF +access+r

Locking the circuit

Basic idea:

1. Define a 4bit * 8 KEY here.
2. Define what key will testbench use here
3. Run testbench with +KEY.
   • ncverilog testfixture.v NFC.v +define+p1+FSDB+KEY +access+r
4. To unlock the circuit, input the 4bit * 8 KEY in correct order.

Example KEY in this repo is PYPD in ascii (python 派對)

Wartermark

When the circuit is in wartermark mode, it writes wartermark on to NAND Flash Memory B repeatly.

To enter wartermark mode, input the following to port KEY in sequence:

• OFSM_KEY_0~OFSM_KEY_6
• WTMK_KEY
• OFSM_KEY_0~OFSM_KEY_7

How to use:

1. Define the parameter:
   1. Define a 8bit * 8 wartermark in NFC.v
   2. Define WTMK_KEY in NFC.v
   3. Also Define WTMK_KEY in testfixture.v
2. Change data in wartermark_mem_goal.dat
3. Run testbench with +WARTERMARK.
   • ncverilog testfixture.v NFC.v +define+p1+FSDB+KEY+WARTERMARK +access+r
   • +KEY must be used with +WARTERMARK

Example Wartermark in this repo is PY party (python party)

TMR

Added the following testing inputs:

• A_ERROR_CTRL
• B_ERROR_CTRL
• C_ERROR_CTRL

When error_ctrl input is 1, the behavier of the module will give wrong outputs.

Added the following output ports:

• TMR_ERROR

When two or more modules gives wrong output, TMR_ERROR outputs 1

1. Run testbench with +TMR.
   • ncverilog testfixture.v NFC_TMR.v +define+p1+FSDB+KEY+TMR +access+r
   • NFC_TMR.v is based on NFC that has KEY function, so +KEY must be used either.

TODO

• Basic functions working
• Locking Circuit
• Obfuscated states
• Wartermarking
• TMR for reliability
• Design a more complex obfuscated states
• Calculate MTTF of the proposed TMR

License

Distributed under the MIT License. See LICENSE for more information.

Authors

• Shinkuan - Shinkuan
• j20020420 - j20020420
• rickhuang31 - rickhuang31