shirishbahirat Goto Github PK

reinforcement-learning-an-introduction

Python Implementation of Reinforcement Learning: An Introduction

reinforcement-learning-introduction

Code from my blog post & online course

ripes

A graphical 5-stage RISC-V pipeline simulator & assembly editor

risc-v-tlm

RISC-V SystemC-TLM simulator

riscv

Verilog implementation of a RISC-V core

riscv-1

RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

riscv-2

riscv-3

RISC-V CPU Core (RV32IM)

riscv-dv

riscv-emu

RISC-V system emulator

riscv-simple-cpu-python

simple riscv

riscv-sodor

educational microarchitectures for risc-v isa

riscv_cpu

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

riscv_em

Simple risc-v emulator, able to run linux, written in C.

riscv_vhdl

VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

rocket-chip

Rocket Chip Generator

serv

SERV - The SErial RISC-V CPU

shakti_custom

testbed for modifications on the family of RISCV processors under the shakti_public bitbucket repository

shirishbahirat.github.io

Blog and information sharing

simulation

simulation

slurm-docker-cluster

A Slurm cluster using docker-compose

soc

development code

spiking-neural-network

Pure python implementation of SNN

sqlglot

Python SQL Parser and Transpiler

stack-vm-tutorials

stateos

Free real-time operating system (RTOS) designed for deeply embedded applications

swerv-iss

Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

symbolic_deep_learning

Code for "Discovering Symbolic Models from Deep Learning with Inductive Biases"

system-design-primer

Learn how to design large-scale systems. Prep for the system design interview. Includes Anki flashcards.