This repo contains Simmani's core implementation as well as its simple examples.
- Power modeling is implemented with Python, which resides in
simmani
. - All Scala code is for example designs generated by Chisel:
GCD
: the Euclide's algorithm for the greatest common divisor (GCD) of two numbers. A.k.a. hello world of hardware.Stack
: hardware implementation of stack.Risc
: simple RISC machine with flip-flop-based memories.RiscSRAM
: simple RISC machine with SRAMs.mini
: RISC-V mini, a 3-stage RISC-V pipeline.
- Each command is executed as follows:
scons --<design> <command>
<design>
is one of examples available above, which ismini
by default. For example, if you want to generate verilog forGCD
, run:scons --GCD rtl-v
. - All CAD tools were run with HAMMER. Due to the NDA, we cannot release code in
tools/hammer-cad-plugins
andtools/hammer-adept-plugins
. - Instead, we provide pre-generated power traces in
power
. RISC-V mini's power traces are available as a tarball due to their sizes.
- SBT
- Python3
- Python packages:
scons
,numpy
,scipy
,matplotlib
,scikit-learn
pip3 install [--user] <package>
- Synopsys VCS
git clone https://github.com/Simmani/simmani.git
cd simmani
./setup.sh # initialize submodules
scons --<design> rtl-v
scons --<design> run-testers
scons --<design> simmani-train
scons --<design> simmani-test
Power training and test results are available in power/<design>/simmani
.
- Donggyu Kim, Jerry Zhao, Jonathan Bachrach, and Krste Asanović, "Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection", In proceedings of the 52nd IEEE/ACM International Symposium on Microarchitecture (MICRO'19), Columbus, OH, October 2019.
- Donggyu Kim, "FPGA-Accelerated Evaluation and Verification of RTL Designs", Ph.D. Thesis, University of California, Berkeley, May 2019.