spacelab-ufsc/interface-board

Interstage Interface Panels

interface-board's Issues

Finish PCB Design Checklist for 1_IIP_Charge board

Create the pcb layout for the 3_IIP_QuadUART schematic sheet

Generate 3D models for v1.0 of Semi USB IIP

Finish PCB Design Checklist for 3_Interface_QuadUART board

Update the mouting holes (remove silkscreen and add larger pad)

Documentation: Update old GOLDs-UFSC mission name and related references

Create the pcb layout for the 2_IIP_RBF schematic sheet

Documentation: Add board images for semi usb variant

Add BomDoc file for each semi usb variant board

Prioritize Mouser and Digi-key suppliers.

Rename project files for N1, N2 and N3 boards

N1 board: 1_Interface_Charge_RBF (old) -> 1_IIP_Charge (new)
N2 board: 2_Interface_JTAG (old) -> 2_IIP_RBF (new)
N3 board: 3_Interface_QuadUART (old) -> 3_IIP_QuadUART (new)

Verify space limit for external and internal connectors

External connectors can cross the P-POD limit and internal connectors can get in the way of cables or inter-board connections like the PC104.

Hardware: Add multi board assembly project

Hardware: Update the boards to the new PCB standard

Define component placement for full USB variant boards

Preliminary planning (without doing any PCB layout yet)

Pcb board 1#: Quad UART using one USB port through FT4232H, four 6 pin picoblade connectors (UART + JTAG connections). This board will be integrated in the -Y side of the 2U CubeSat structure.

Pcb board 2#: Double JTAG using one USB port through FT4232H and two picoblade 4 pin for interfacing JTAG and UART signals with pcb board 1º. This board will be integrated in the -X side of the 2U CubeSat structure.

Pcb board 3#: Double JTAG using one USB port through FT4232H and two picoblade 4 pin for interfacing JTAG and UART signals with pcb board 1º. This board will be integrated in the +Y side of the 2U CubeSat structure.

Pcb board 4#: 4 pin power header for charging batteries. This board will be integrated in the +X side of the 2U CubeSat structure.

Note: pcb board 3º and 4º will have the same circuit.

Make USB low pass filter for USB 2.0 VBUS line

The recommended filter circuit can be found on the 14 page of the "AN_146 USB Hardware Design Guidelines for FTDI ICs" document.

Doc: Add a image presenting the placement/attachment relative to the structure

Reference image:
https://github.com/andrempmattos/cubesat-solar-panels/blob/main/documentation/figures/15.png

Add it in the main readme too.

Note: This issue is non-critical.

Hardware: Delete extra assembly layer on LQFP-64 footprint

Documentation: Update contributing authors list

Finish PCB Design Checklist for 2_IIP_RBF board

Generate .step files of minimal interface PCB setup for mechanical evaluation

"Minimal interface PCB setup" means the essential PCB boards composed from 1_Interface_Charge_RBF and 2_Interface_JTAG PCB documents.

Doc: update all tex source files description

Update version control, contact information and main titles.

Doc: change pdf output name to new document ID

Change to "slb-iip-doc-v1.0.pdf"
https://github.com/spacelab-ufsc/docs-tracking/blob/main/docs.csv

Update the SpaceLab logo

Update the SpaceLab logo on the boards for the next release.

Define ESD protection circuit for USB 2.0 header in board N3

N3 board is refering to 3_Interface_QuadUART PCB.

Some sources found for guidance:
https://www.ftdichip.com/Support/Documents/AppNotes/AN_146_USB_Hardware_Design_Guidelines_for_FTDI_ICs.pdf
USB 2.0 Board Design and Layout Guidelines.pdf

Update readme of "root" directory

Create the "3_IIP_QuadUART" schematic sheet

This schematic will have a FT4232H with four UART channels through a mini B USB port, four 6 pin picoblade connectors for UART and JTAG connections.

Make Schematic Library

Hardware: Space components of the IIP Nº3 board

This might make it easier to assembly by hand if needed.

Create the docummentation for the project

Update the general block diagram to include the fourth iip board

Create the "1_IIP_Charge" schematic sheet

Create the "2_IIP_RBF" schematic sheet

This schematic will have four JTAG headers 5 line and double row pins (5x2) compatible with standard Texas Instruments CC Debugger cable connector, four picoblades 4 pin for interfacing JTAG and UART signals with the quad UART pcb and one 4 pin power header for charging batteries.

Fix fiducials small bottom solder

The fiducials are placed in all the boards of the project board for convenience.

Documentation: Write about the connectors height constraint

Create the "0_Architecture" schematic sheet

Hardware: add draftsman files for all boards of semi USB variant

Define architecture and topology

Create block diagram of the project and core schematic files.

Define the use (or not) of an external EEPROM for FT4232H

Hardware: Create the fourth pcb board of IIP

It should be named "4_iip_closure".

Hardware: Update imagens, diagrams, and templates to "embbeded source"

In properties enable the embedded option, since it works in any computer and file system in case of non-attachment of the source images.

Create the pcb layout for the 1_IIP_Charge schematic sheet

Update PDF files with new collaborators for IIP Semi USB

Readme: Update main, hardware and documentation README files

Generate 3D models of N1 and N2 boards for second mechanical evaluation

N1 board: 1_Interface_Charge_RBF.PcbDoc
N2 board: 2_Interface_JTAG.PcbDoc

Changes made from first mechancial evaluation:

1. Removed 1mm of heigh and shorted the distance from mechanical holes by 1mm on both boards;
2. Removed 7,5 mm from both sides on N2 board;

Fix picoblade header positioning in N1 and N2 boards

Example is portaited below, the X marked picoblade header on the image must be removed according to #26. Only the FT4232H picoblade (right side of the pic) must be moved in N2 board.

Move RBF pin header from N1 to N2 board

Currently the N1 board (1_Interface_Charge_RBF to be mounted in the -Y plane) has a 2 pin header for RBF switch, for the correct integration in the P-POD it must be moved to the N2 board (2_Interface_JTAG to be mounted in the -X plane).

Source: https://static1.squarespace.com/static/5418c831e4b0fa4ecac1bacd/t/56e9b62337013b6c063a655a/1458157095454/cds_rev13_final2.pdf

Make PCB Library

Hardware: Move the tests points away from the "structure contact area" of the PCBs

Generate first output files for IIP semi USB

The files to be generated for each three boards (N1, N2 and N3) are:

• .OutJob file configuration
• BOM.xls
• SCH.pdf
• GERBERS.zip
• NC Drill files.zip
• Pick and Place files.zip
• ODB++.zip

Define component placement for semi USB variant boards

The components placement needs to take into consideration the maximum 6.5mm external distance beyong the default 100mm of the X and Y plane. Depending on the mouting of the PCB on front or inside the 2U CubeSat structure, the height limit of external connectors can vary (pcb thickness + structure thickness).
The semi USB variant uses individual connectors for interfacing JTAG into each module.