sparkfun/edison_adc_block

Adds four single-ended or two differential ADC channels to the Edison.

SparkFun Block for Intel Edison - ADC

SparkFun Block for Intel Edison - ADC (DEV-13770)

This card adds ADC functionality to the Edison's I²C bus. The ADS1015 ADC from TI provides a single 12-bit delta-sigma convertor with an analog multiplexer. It can be configured as a four-channel single-ended device or as a two-channel differential device.

The board has jumpers to allow selection of the I²C slave address among four different options, allowing up to four of these cards to be stacked under one Edison. The sampling rate is not sufficient for audio capture, at 2.2kHz, but it should be adequate for most control applications.

Repository Contents

• /Hardware - Eagle design files (.brd, .sch)
• /Production - Production panel files (.brd)

Documentation

• Hookup Guide - Basic hookup guide for the Edison ADC Block.
• SparkFun Fritzing repo - Fritzing diagrams for SparkFun products.
• SparkFun 3D Model repo - 3D models of SparkFun products.

Version History

• v21 - Version 2.1. Currently for sale. Fixes noise on the ADC lines, adds locking header footprint.
• v20 - Version 2.0. Retired.
• v10 - Original release. Retired.

License Information

This product is open source!

Please review the LICENSE.md file for license information.

If you have any questions or concerns on licensing, please contact [email protected].

Distributed as-is; no warranty is given.

• Your friends at SparkFun.

edison_adc_block's Issues

Component names and values

PCA needs Tname and Tvalue in BRD

Hirose needs Tname and Tvalue in BRD

MIC VREG needs value in SCH

V20 Checklist Issues

Got an air wire on the HIROSE connectors (top and bottom), looks like the GND pour doesn't want to make a connection. Upper right of the connector

Check the silk I added

I removed the per-pin silk and added a table with the pertinent differential pin information. Check it and see if it matches expectations.

Flag label needed

I think it would be nice to add a flag label to the VREF net connected to the 8-pin header, purely for the ease of reading/interpretation.

Right now it does not have any visible label.

Move polarity mark silk outside package footprint

-Connector
-IC

Regulator stability

The 3.3V reference rail is bouncing all over the place, the same thing we saw with the FreeSoC2.

I tried a 2.2uF cap on there, as we've got on the FreeSoC, but no luck.

Probably going to have to find a higher ESR small package tant for this. Also, going to need another proto round to verify it.

Copper Pour Isolate

Currently set to 2mil instead of 12mil.

if this is intentional, disregard.

Connections outside suggested footprint area.

Why are the connections so far away from the board? Can we bring them into the suggested footprint? Max board length is for connectors that exceed stack height limits. AKA Servo/motor/power/interfaces

Revised by?

Do we want a revised by element added to the SCH and BRD for this design?

if not, disregard.

ADC Block V20 Proto Checklist #2 Issues

(1) Looks like there is a mix and match of different sized traces around the PCA (some .01" and some .006"). The .006" traces going to the Hirose are okay, but I think we could go up to .01" on some of the smaller traces that do not lead to the Hirose.

As of now I think functionality should be fine, but for consistency, it may be worth changing some of the trace sizes; up to you.

(2) Can you add a line/polygon of "Trestrict" to the side of the GND pad on the PCA to get rid of the GND hash mark on the side of the pad. (Between SDA1 and GND)

(3) The measurement graphics are on "TDocu" instead of the "Measures" layer; up to you.

Board dimension thickness

Noticed that the board dimension thickness is 6mil instead of 8mil.

If this is intentional disregard.