ProASIC3 port

[stnolting]

ProASIC3 port

[stnolting]

When you disable a certain optional module (like the GPIO unit) only the actual core logic gets discarded. Of course the top level ports are still there but there is no more logic driving/reading them.

I would suggest to use a wrapper instead of directly using neorv32_top.vhd as top entity.
There are some wrappers available in https://github.com/stnolting/neorv32/tree/master/rtl/top_templates

For example, the neorv32_test_setup.vhd is a very simple wrapper only propagating the UART and GPIO ports to FPGA pins.

The compiler tools are linux only. Do I need WSL or should I be able to find some pre-built windows executables?

I have tried WSL and it is a bit unstable... I am using Ubuntu on Windows and that works pretty well.

There are pre-built toolchains for Windows out there. Maybe you could use the version from SiFive, but I haven't tried that yet.

[rcaproni]

Hi Guys: About the compiler, I´m using windows only. I Installed the compiler from here: https://xpack.github.io/riscv-none-embed-gcc/install/ The version I´m using is 8.3.0-1.2.1 To compile using the makefile, you will need some modification: - Install gcc riscv using XPACK - Compile image_gen for windows (I used mingw64) and put in the image_gen folder - Edit makefile # Compiler toolchain XPACK_TOOLCHAIN ?= C:/Users/riscv/AppData/Roaming/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/8.3.0-1.2.1/.content RISCV_TOOLCHAIN ?= $(XPACK_TOOLCHAIN)/bin/riscv-none-embed Disable image_gen compilation #$(IMAGE_GEN): $(NEORV32_EXG_PATH)/image_gen.cpp # @echo Compiling $(IMAGE_GEN) # @$(CC_X86) $< -o $(IMAGE_GEN) With these modifications you can use windows to compile and you will have the .bin file to upload to the board. I´ve been using it for months. Regards Rodolfo Em qui., 1 de out. de 2020 às 11:12, Stephan <[email protected]> escreveu:

…

When you disable a certain optional module (like the GPIO unit) only the actual core logic gets discarded. Of course the top level ports are still there but there is no more logic driving/reading them. I would suggest to use a wrapper instead of directly using neorv32_top.vhd as top entity. There are some wrappers available in https://github.com/stnolting/neorv32/tree/master/rtl/top_templates For example, the neorv32_test_setup.vhd <https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd> is a very simple wrapper only propagating the UART and GPIO ports to FPGA pins. The compiler tools are linux only. Do I need WSL or should I be able to find some pre-built windows executables? I have tried WSL and it is a bit unstable... I am using Ubuntu on Windows <https://ubuntu.com/tutorials/ubuntu-on-windows#1-overview> and that works pretty well. There are pre-built toolchains for Windows out there. Maybe you could use the version from SiFive <https://www.sifive.com/software>, but I haven't tried that yet. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#1 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AJJNPLYMTR6BSXJDWH72WLDSISE6PANCNFSM4SAJPLBQ> .

-- "Quis custodiet ipsos custodes?" ("Quem vigia os vigilantes?") Juvenal - Sátiras livro VI

[salmansheikh]

The compiler tools are linux only. Do I need WSL or should I be able to find some pre-built windows executables?

[salmansheikh]

Yes, I a colleague reminded me of the SiFive stuff but I downloaded and my works symantec for some reason flagged all the files after I extracted them and added them to my windows path. I am trying the WSL route as I used it on my old laptop at work. I heard WSL 2 is better but in beta and looks to be a pain (for admins) to go through hoops to install.

I didn't look at the templates. I thought those were from the Lattice and Vivado only. I will use one of those next time. I got a simple design with just SPI and UART compiled and ready to program the Microsemi board. I may bring some GPIO for the LEDs before I do that.

Thanks.

[salmansheikh]

Hi Guys: About the compiler, I´m using windows only. I Installed the compiler from here: https://xpack.github.io/riscv-none-embed-gcc/install/ The version I´m using is 8.3.0-1.2.1 To compile using the makefile, you will need some modification: - Install gcc riscv using XPACK - Compile image_gen for windows (I used mingw64) and put in the image_gen folder - Edit makefile # Compiler toolchain XPACK_TOOLCHAIN ?= C:/Users/riscv/AppData/Roaming/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/8.3.0-1.2.1/.content RISCV_TOOLCHAIN ?= $(XPACK_TOOLCHAIN)/bin/riscv-none-embed Disable image_gen compilation #$(IMAGE_GEN): $(NEORV32_EXG_PATH)/image_gen.cpp # @echo Compiling $(IMAGE_GEN) # @$(CC_X86) $&lt; -o $(IMAGE_GEN) With these modifications you can use windows to compile and you will have the .bin file to upload to the board. I´ve been using it for months. Regards Rodolfo Em qui., 1 de out. de 2020 às 11:12, Stephan [email protected] escreveu:
…
When you disable a certain optional module (like the GPIO unit) only the actual core logic gets discarded. Of course the top level ports are still there but there is no more logic driving/reading them. I would suggest to use a wrapper instead of directly using neorv32_top.vhd as top entity. There are some wrappers available in https://github.com/stnolting/neorv32/tree/master/rtl/top_templates For example, the neorv32_test_setup.vhd https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd is a very simple wrapper only propagating the UART and GPIO ports to FPGA pins. The compiler tools are linux only. Do I need WSL or should I be able to find some pre-built windows executables? I have tried WSL and it is a bit unstable... I am using Ubuntu on Windows https://ubuntu.com/tutorials/ubuntu-on-windows#1-overview and that works pretty well. There are pre-built toolchains for Windows out there. Maybe you could use the version from SiFive https://www.sifive.com/software, but I haven't tried that yet. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#1 (comment)>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AJJNPLYMTR6BSXJDWH72WLDSISE6PANCNFSM4SAJPLBQ .
-- "Quis custodiet ipsos custodes?" ("Quem vigia os vigilantes?") Juvenal - Sátiras livro VI

Thanks but I am using a work computer and don't have elevated privileges so I may go with WSL for now. This is more involved. On my home machine, I can do these easily .Heck my home machine is an Ubuntu. No windows here..

[salmansheikh]

I didn't have gcc or g++ installed. I thought they would be installed by default. now the toolchain works and I can build examples. Onwards!!!

[stnolting]

@rcaproni Nice solution for Windows! I did not know https://xpack.github.io/riscv-none-embed-gcc/install/. I definitively have to try that out.

[rcaproni]

@rcaproni Nice solution for Windows! I did not know https://xpack.github.io/riscv-none-embed-gcc/install/. I definitively have to try that out.

Yes, good solution provided by mcu-eclipse guys. Works fine for NEORV.